w83977eg Winbond Electronics Corp America, w83977eg Datasheet - Page 59

• Manufacturer Part Number: w83977eg
• Description: Winbond Isa I/o W83977ef W83977eg
• Manufacturer: Winbond Electronics Corp America

7.2.5
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting)
and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP
data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the
EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of
cycle to be performed and the data to be output to the host CPU.
7.2.6
Data Port (R/W)
Status Buffer (Read)
Control Swapper (Read)
Control Latch (Write)
EPP Address Port R/W)
EPP Data Port 0 (R/W)
EPP Data Port 1 (R/W)
EPP Data Port 2 (R/W)
EPP Data Port 3 (R/W)
REGISTER
EPP Data Port 0-3
Bit Map of Parallel Port and EPP Registers
BUSY#
PD7
PD7
PD7
PD7
PD7
PD7
7
1
1
ACK#
7
PD6
PD6
PD6
PD6
PD6
PD6
6
1
1
6
PD5
PD5
PD5
PD5
PD5
PD5
DIR
PE
5
5
1
W83977EF-AW/W83977EG-AW
4
IRQEN
SLCT
PD4
PD4
PD4
PD4
PD4
PD4
IRQ
3
4
-57-
2
ERROR#
1
SLIN
SLIN
PD3
PD3
PD3
PD3
PD3
PD3
3
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Publication Release Date: Apr. 2006
INIT#
INIT#
PD2
PD2
PD2
PD2
PD2
PD2
2
1
IOR#
AUTOFD#
AUTOFD#
PD1
PD1
PD1
PD1
PD1
PD1
causes an EPP read
1
1
Revision 1.2
STROBE#
STROBE#
TMOUT
PD0
PD0
PD0
PD0
PD0
PD0
0