w83977eg Winbond Electronics Corp America, w83977eg Datasheet - Page 66

• Manufacturer Part Number: w83977eg
• Description: Winbond Isa I/o W83977ef W83977eg
• Manufacturer: Winbond Electronics Corp America

Bit 4: Read/Write (Valid only in ECP Mode)
Bit 3: Read/Write
Bit 2: Read/Write
Bit 1: Read only
Bit 0: Read only
7.3.11 Bit Map of ECP Port Registers
Notes :
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
1
0
1
0
1
0
0
1
0
1
Addr/RLE
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
compress
nBusy
PD7
D7
Disables the interrupt generated on the asserting edge of nFault.
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
Enables DMA.
Disables DMA unconditionally.
Disables DMA and all of the service interrupts.
Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to
0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr
Threshold or more bytes free in the FIFO.
(c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr
Threshold or more valid bytes to be read from the FIFO.
The FIFO has at least 1 free byte.
The FIFO cannot accept another byte or the FIFO is completely full.
The FIFO contains at least 1 byte of data.
The FIFO is completely empty.
1
0
Address or RLE field
intrValue
MODE
nAck
PD6
D6
1
0
Directio
PError
PD5
D5
1
0
W83977EF-AW/W83977EG-AW
nErrIntrEn
ackIntEn
Select
PD4
D4
-64-
1
1
SelectIn
dmaEn
nFault
PD3
D3
0
1
serviceIntr
PD2
nInit
D2
1
0
1
autofd
PD1
D1
full
1
0
1
strobe
empty
PD0
D0
1
0
1
NOTE
2
1
1
2
2
2