psd311-b-90ui STMicroelectronics, psd311-b-90ui Datasheet - Page 26

• Manufacturer Part Number: psd311-b-90ui
• Description: Low Cost Field Programmable Microcontroller Peripherals
• Manufacturer: STMicroelectronics

12.0
Control Signals
(cont.)
12.5 A19/CSI
This pin is configured using PSDsoft to be either a chip select for the entire PSD device or
an additional PAD input. If your MCU can generate a chip-select signal, and you wish to
save power, use the PSD chip select feature. Otherwise, use this pin as an address or logic
input.
Table 7A. Signal States During Power-Down Mode
Table 7B. Internal States During Power-down
NOTE: N/A = Not Applicable
PAD A and PAD B
All registers in CSIOPORT
address space, including:
Port Pins PC0–PC2
AD0–A0/AD15/A15
Port Pins PB0–PB7
Port Pins PA0–PA7
When configured as CSI (active-low PSD chip select): a low on this pin keeps the PSD
in normal operation. However, when a high is detected on the pin, the PSD
enters Power-down Mode. See Tables 7A and 7B for information on signal states
during Power-down Mode. See section 16 for details about the reduction of power
consumption.
When configured as A19, the pin can be used as an additional input to the PADs.
It can be used for address or logic. It can also be ALE/AS dependent or a transparent
input, which is determined by your PSDsoft design file. In A19 mode, the PSD is always
enabled.
Direction
Data
Page
PMR (turbo bit, ZPSD only)
Port
Component
All
MCU I/O
Tracking AD0/A0-AD7/A7
Latched Address Out
MCU I/O
Chip Select Outputs, CS0–CS7, CMOS
Chip Select Outputs, CS0–CS7, Open Drain
Address or Logic Inputs, A16-A18
Chip Select Outputs, CS8–CS10, CMOS only
Configuration Mode(s)
CS0–CS10
CSADIN, CSADOUT1,
CSADOUT2, CSIOPORT,
ES0-ES7, RS0
N/A
Internal Signal
Internal Signal State
During Power-Down
Logic 1 (inactive)
Logic 0 (inactive)
All unchanged
PSD3XX Family
Input (Hi-Z)
Unchanged
Input (Hi-Z)
Unchanged
Input (Hi-Z)
Logic 1
Logic 1
Logic 1
State
Hi-Z
23