sle24c16-s ETC-unknow, sle24c16-s Datasheet - Page 12

• Manufacturer Part Number: sle24c16-s
• Description: 8/16 Kbit 1024/2048 Serial Cmos Eeproms, Synchronous 2-wire
• Manufacturer: ETC-unknow

Semiconductor Group
5.2
Address Setting
Transmission of Data
Programming Cycle
Those bytes of the page that have not been addressed are not included in the
programming.
Figure 8
Page Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for
speed enhancement in order to indicate the end of the erase/write cycle (refer to
chapter 5.3 Acknowledge Polling).
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
Page Write
R
S
T
A
T
S
Command Byte
CSW
0
The page write procedure is the same as the byte write
procedure up to the first data byte. In a page write instruction
however, entry of the EEPROM address byte EEA is followed
by a sequence of one to maximum sixteen data bytes with the
new data to be programmed. These bytes are transferred to
the internal page buffer of the EEPROM.
The first entered data byte will be stored according to the
EEPROM address n given by EEA (A0 to A7) and CSW (A8 to
A9 or A10). The internal address counter is incremented
automatically after the entered data byte has been
acknowledged. The next data byte is then stored at the next
higher EEPROM address. EEPROM addresses within the
same page have common page address bits A4 through A10.
Only the respective four least significant address bits A0
through A3 are incremented, as all data bytes to be
programmed simultaneously have to be within the same page.
The master stops data entry by applying a STOP condition,
which also starts the internally timed erase/write cycle. In the
first step, all selected bytes are erased to “1”. With the next
internal step, the addressed bytes are written according to the
contents of the page buffer.
C
K
A
EEPROM Address
EEA n
A
C
K
12
Data Byte n
C
K
A
Data Byte n+1
C
K
A
Data Byte n+15
SLx 24C08/16
1998-07-27
IED02140
A
C
K
O
S
P
P
T