sle24c16-s ETC-unknow, sle24c16-s Datasheet - Page 16

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sle24c16-s

Manufacturer Part Number
sle24c16-s
Description
8/16 Kbit 1024/2048 Serial Cmos Eeproms, Synchronous 2-wire
Manufacturer
ETC-unknow
Datasheet
Semiconductor Group
6.2
The EEPROM content is read without setting an EEPROM address, in this case the
current content of the address counter will be used (e.g. to continue a previous read
operation after the Master has served an interrupt).
Transmission of CSR
Transmission of
EEPROM Data
STOP Condition from
Master
Figure 12
Current Address Read
Current Address Read
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
For a current address read the master generates a START
condition, which is followed by the command byte CSR (chip
select read). The receipt of the CSR-byte is acknowledged by
the EEPROM with a low on the SDA line.
During the next eight clock pulses the EEPROM transmits the
data byte and increments the internal address counter.
During the following clock cycle the masters releases the bus
and then transmits the STOP condition.
R
S
T
A
T
S
Command Byte
CSR
16
1
K
A
C
Data Byte
IED02132
O
P
P
S
T
SLx 24C08/16
1998-07-27

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