adg733 Analog Devices, Inc., adg733 Datasheet - Page 6

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adg733

Manufacturer Part Number
adg733
Description
Cmos, 2.5  Low Voltage, Triple/quad Spdt Switches
Manufacturer
Analog Devices, Inc.
Datasheet

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ADG733/ADG734
V
V
I
I
GND
S
D
A
EN
V
R
∆R
R
I
I
V
V
I
C
C
C
t
t
t
t
t
Charge
Off Isolation
Crosstalk
On Response
Insertion Loss
A2
X
0
0
0
0
1
1
1
1
X = Don’t Care.
ON
OFF
ON
OFF
OPEN
DD
SS
S
D
INL
DD
SS
D
INL
INH
X
ON
FLAT(ON)
S
D
IN
, I
(OFF)
ON
, C
(OFF)
(EN)
(V
(I
(EN)
S
INH
(ON)
S
S
)
(ON)
)
A1
X
0
0
1
1
0
0
1
1
Table I. ADG733 Truth Table
A0
X
0
1
0
1
0
1
0
1
Most Positive Power Supply Potential
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to
ground close to the device.
Positive Supply Current
Negative Supply Current
Ground (0 V) Reference
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input
Active low device enable
Analog Voltage on Terminals D and S
Ohmic Resistance between D and S
On Resistance Match between any Two Channels (i.e., R
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over
the specified analog signal range.
Source Leakage Current with the Switch “OFF”
Channel Leakage Current with the Switch “ON”
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Input Current of the Digital Input
“OFF” Switch Source Capacitance. Measured with reference to ground.
“ON” Switch Capacitance. Measured with reference to ground.
Digital Input Capacitance
Delay Time Measured between the 50% and 90% Points of the Digital Inputs and the Switch “ON” Condition
Delay Time Measured between the 50% and 90% Points of the Digital Input and the Switch “OFF” Condition
Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “ON” Condition
Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “OFF” Condition
“OFF” Time Measured between the 80% Points of Both Switches when Switching from One Address State to
Another
A Measure of the Glitch Impulse Transferred Injection from the Digital Input to the Analog Output during Switching
A Measure of Unwanted Signal Coupling through an “OFF” Switch.
A Measure of Unwanted Signal that Is Coupled through from One Channel to Another as a Result of Para-
sitic Capacitance
The Frequency Response of the “ON” Switch
The Loss Due to the On Resistance of the switch
EN
1
0
0
0
0
0
0
0
0
ON Switch
None
D1-S1A, D2-S2A, D3-S3A
D1-S1B, D2-S2A, D3-S3A
D1-S1A, D2-S2B, D3-S3A
D1-S1B, D2-S2B, D3-S3A
D1-S1A, D2-S2A, D3-S3B
D1-S1B, D2-S2A, D3-S3B
D1-S1A, D2-S2B, D3-S3B
D1-S1B, D2-S2B, D3-S3B
TERMINOLOGY
–6–
ON
max and R
Logic
0
1
Table II. ADG734 Truth Table
ON
min)
Switch A
OFF
ON
Switch B
ON
OFF
REV. A

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