W230 Cypress Semiconductor Corp., W230 Datasheet
W230
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W230 Summary of contents
Page 1
... HIGH. Pin function with parentheses determined by MODE pin 24_48MHz/FS3 resistor strapping. Unlike other I/O pins, input FS3 has an internal VDDQ3 pull-down resistor. SDRAM0:12 13 • 3901 North First Street • San Jose W230 CPUT_CS CPUT0 PCI 0:5 Spread (MHz) (MHz) Spectrum 1 1 100.0 33.3 – ...
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... Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24/48-MHz output. Connect to 3.3V supply Ground Connections: Connect all ground pins to the common system ground plane. 2 W230 ...
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... Control Logic Figure 2. Input Logic Selection Through Jumper Option Upon W230 power-up, the first operation is used for input logic selection. During this period, the five I/O pins (7, 8, 25, 26, 48) are three-stated, allowing the output strapping re- sistor on the l/O pins to pull the pins and their associated ca- pacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “ ...
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... Spread Spectrum clocking is activated or deactivated by se- lecting the appropriate values for bits 1–0 in data byte 0 of the data stream. Refer to Table 6 for more details. 7\SLFDO &ORFN Spread Spectrum Enabled Figure 4. Typical Modulation Profile 4 W230 EMI Reduction Non- Spread Speactrum Frequency Span (MHz) Down Spread ...
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... No user application. Register bit must be writ- ten as 0. Byte Description Commands the W230 to accept the bits in Data Bytes 0–6 for internal register configuration. Since other devices may exist on the same com- mon serial data bus necessary to have a specific slave address for each potential receiver ...
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... Control Function 0 -- Hardware Normal -- -- -- -- -- -- -- -- -- Low -- Low Low Low Low Low -- 24-MHz Low Low -- Low 6 W230 Bit Control 1 Default -- 0 See Table 6 0 See Table 6 0 See Table 6 0 Software 0 See Table 6 1 See Table 6 0 Three-stated ...
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... Data Byte (Reserved (Reserved (Reserved (Reserved (Reserved (Reserved (Reserved (Reserved) Control Function 0 Low Low -- -- -- -- -- -- -- -- -- -- -- -- -- -- Low Low -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 7 W230 Bit Control 1 Default Active 1 Active Active 1 Active ...
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... W230 Output Frequency PCI Spread Spectrum 33.3 –0.5% 33.3 ±0.25% [ 33.3 0.5% 31.7 OFF 33.3 –0.5% 33.3 ±0.25% [ 33.3 0.5% 34.0 OFF 34.6 OFF 35.3 OFF 35.6 OFF 36.0 OFF 36.3 OFF 36.6 OFF 37.0 OFF 37 ...
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... W230 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device. above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability ...
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... DD 5. The W230 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). ...
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... Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. Average value during switching transition. Used for determining series termination value. 11 W230 Min. Typ. Max. Unit ...
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... Length = 5” Figure 5. K7 Open Drain Clock Driver Test Circuit Package Type 48-pin SSOP (300 mils) 12 Min. Typ. Max. 24.004 +167 57/34 0 Length = 3 ” T2 20p 1. Length = 3 ” T5 20p W230 Unit MHz ppm V/ns V/ ...
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... C1, C3 & 10– & 0.005 VIA to GND plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors V DDQ3 DDQ3 Core 0 =VIA to respective supply plane layer 13 W230 V DDQ3 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W230 ...