W233 Cypress Semiconductor Corp., W233 Datasheet - Page 13
W233
Manufacturer Part Number
W233
Description
Spread Spectrum FTG For Via Mobile K7 Chipset
Manufacturer
Cypress Semiconductor Corp.
Datasheet
1.W233.pdf
(16 pages)
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24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Ordering Information
Document #: 38-07250 Rev. **
f
f
m/n
t
t
t
f
Z
W233
Parameter
D
R
F
D
ST
o
Ordering Code
Frequency, Actual
Deviation from 24 MHz
PLL Ratio
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
AC Output Impedance
Clock Chip
CPUDriver
CPUCLK_T
CPUCLK_C
Description
Package
Name
H
R8
47
R9
47
PRELIMINARY
Figure 5. K7 Open Drain Clock Driver Test Circuit
48-pin SSOP (300 mils)
Determined by PLL divider ratio (see m/n below)
(24.004 – 24)/24
(14.31818 MHz x 57/34 = 24.004 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching transition. Used
for determining series termination value.
Package Type
Test Condition/Comments
3.3
Z0 = 52
Length = 5”
T1
Z0 = 52
Length = 5”
T4
-
+
V1
VDD
Z0 = 52
Length = 3
Z0 = 52
Length = 3
T2
T5
1.5V
”
1.5V
”
R1
68
R3
68
Min.
20p
20p
0.5
0.5
45
24.004
57/34
+167
Typ.
40
Max.
Page 13 of 16
55
2
2
3
W233
MHz
V/ns
V/ns
Unit
ppm
ms
%