tc74ac112 TOSHIBA Semiconductor CORPORATION, tc74ac112 Datasheet

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... TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC112P,TC74AC112F,TC74AC112FN Dual J-K Flip Flop with Preset and Clear The TC74AC112 is an advanced high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C MOS technology achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation ...

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... Don’t care System Diagram Outputs Function Clear H L Preset Change Toggle Change TC74AC112P/F/FN 2007-10-01 ...

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... 500 (DIP) (Note 2)/180 (SOP) D −65 to 150 T stg Symbol Rating V 2 OUT CC − opr = 3.3 ± 0 100 (V CC dt/ ± 0 TC74AC112P/F/FN Unit °C Unit °C ns/V 2007-10-01 ...

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... 3 4 (Note) 5 GND 5 GND 5 TC74AC112P/F/ − 25°C 85°C Min Typ. Max Min Max ⎯ ⎯ ⎯ 1.50 1.50 ⎯ ⎯ ⎯ 2.10 2.10 ⎯ ⎯ ⎯ 3.85 3.85 ⎯ ⎯ ⎯ 0.50 0.50 ⎯ ⎯ ⎯ ...

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... Test Condition V (V) CC 3.3 ± 0.3 ⎯ 5.0 ± 0.5 3.3 ± 0.3 ⎯ 5.0 ± 0.5 3.3 ± 0.3 ⎯ 5.0 ± 0.5 ⎯ ⎯ (per F/ TC74AC112P/F/ −40 to 25°C 85°C V (V) Limit Limit CC 3.3 ± 0.3 7.5 7.5 5.0 ± 0.5 5.0 5.0 3.3 ± 0.3 7.0 7.0 5.0 ± 0.5 5.0 5.0 3.3 ± 0.3 11.0 11.0 5.0 ± 0.5 6.0 6.0 3.3 ± 0.3 ...

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... Package Dimensions Weight: 1.00 g (typ.) TC74AC112P/F/FN 6 2007-10-01 ...

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... Package Dimensions Weight: 0.18 g (typ.) TC74AC112P/F/FN 7 2007-10-01 ...

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... Package Dimensions (Note) Note: This package is not available in Japan. Weight: 0.13 g (typ.) TC74AC112P/F/FN 8 2007-10-01 ...

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... Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. TC74AC112P/F/FN 9 20070701-EN GENERAL 2007-10-01 ...