pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 24

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

With the following instruction sequence
00000001
11111111
10101010
the byte sequence
11001110
00000000
10101010
can be read.
The CM location AA
Bits 7, 6, 3, 2, of the control byte showing logical 0 in the first byte at the beginning of the read
access reappear as logical 1 in the fourth byte. This is due to the internal device architecture. These
bits are unused and are recommended to be set to logical 0 to avoid future incompatibility problems.
In CSR and CFR read accesses, bit 1 and bit 0 (C1 and C0) of the read control byte have a value
of logical 1.
Register Contents
You will find a detailed description of the different register contents in section 4. This paragraph
only gives a short overview of the different registers:
The mode register contains bits to determine the operation mode and the output tristating scheme,
to control the CM reset mechanism, to interrupt the indirect access mechanism and to switch the
chip to standby.
The status register consists of 3 bits. They tell whether the PEx 2045 is busy resetting its connection
memory or performing an indirect access or whether operational conditions have occurred which
might lead to a partial or complete loss of data in the connection and speech memory. Bits 4 to 0 of
the status register default to logical 0.
The clock shift register holds information on how the frame structure is advanced or delayed relative
to the synchronization pulse. It is only active for the system interface in the primary access
configuration. See chapter 2.4. In standard configuration it is set to logical 0.
The configuration register is used to select the device clock frequency and the configuration in
which the device is used. The most significant 6 bits default to logical 1, if the register is read.
The connection memory content and address contain the connection information. Specifics are
explained in the following sections.
Semiconductor Group
A0 = 1, WR = 0, RD = 1, CS = 0
A0 = 1, WR = 1, RD = 0, CS = 0
H
, which has been written to 200
24
H
in the last example is read again.
PEB 2045
PEF 2045