pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 30

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

3
3.1
Upon power up the PEx 2045 is set to its initial state. The mode and configuration register bits are
all set to logical 1, the clock shift register bits to logical 0. The status register B bit is undefined, the
Z bit contains logical 0, the R bit is undefined.
This state is also reached by pulling the WR and RD signals to logical 0 at the same time (software
reset). For the software reset the state of CS is of no significance.
3.2
After power up a few internal signals and clocks need to be initialized. This is done with the
initialization sequence. To give all signals and clocks a defined value the MTSC must encounter 3
falling and 2 rising edges of the SP signal. The resulting SP pulses may be of any length allowed in
normal operation, the time interval between the two SP pulses may be of any length down to 250 ns.
With all signals being defined, the CM needs to be reset. To do that a logical 0 is written into
MOD:RC. STA:B is set. The resulting CM reset is finished after at most 250 s and is indicated by
the status register B bit being logical 0. Changing the pulse shaping factor N during CM reset may
result in a CM-reset time longer than 250 s.
To prepare the PEx 2045 for programming the CM, the RI bit in the mode register must be reset.
Note that one mode register access can serve to reset both RC and RI bits as well as configuring
to chip (i.e. selecting operating mode etc.).
Figure 18
Initializing the PEx 2045 for a 8192-kHz Device Clock
Semiconductor Group
Operational Description
Power Up
Initialization Procedure
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PEB 2045
PEF 2045