pef80913 Infineon Technologies Corporation, pef80913 Datasheet - Page 83
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pef80913
Manufacturer Part Number
pef80913
Description
2b1q Second Gen. Modular Isdn Nt
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF80913.pdf
(240 pages)
- Current page: 83 of 240
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Table 17
Hex-
code
i1-i8
51
52
53
54
AA
FF
XX
2.4.3.2
The on-chip EOC-processor is responsible for the correct insertion and extraction of
EOC-data on the U-interface. The EOC-processor can be programmed either to auto
mode or to transparent modes (see
Figure 38
and received.
Data Sheet
D
LB1
LB2
RCC
NCC
RTN
shows the registers and pins that are involved when EOC data is transmitted
EOC Processor
Usage of Supported EOC-Commands(cont’d)
U
UTC Unable to comply. Message sent instead of an
ACK Acknowledge. If a defined and correctly addressed EOC-
Function
Closes B1 loop-back in NT. All B1-channel data will be
looped back within the Q-SMINT I U-transceiver. The bits LB1
and U/IOM are set in the register LOOP.
Closes B2 loop-back in NT. All B2-channel data will be
looped back within the Q-SMINT I U-transceiver. The bits LB2
and U/IOM are set in the register LOOP.
Request corrupt CRC. Upon receipt the Q-SMINT I transmits
corrupted (= inverted) CRCs upstream. This allows to test the
near end block error counter on the LT-side. The far end block
error counter at the Q-SMINT I-side is stopped and Q-
SMINT I-error indications are retained.
Notify of corrupt CRC. Upon receipt of NCC the Q-SMINT I-
block error counters (near-end only) are disabled and error
indications are retained. This prevents wrong error counts
while corrupted CRCs are sent.
acknowledgment if an undefined EOC-command or d/m bit=0
was received by the Q-SMINT I.
Return to normal. With this command all previously sent
EOC-commands will be released. The EOCW register is reset
to its initial state (FF
command was received by the Q-SMINT I, the Q-SMINT I
replies by echoing back the received command.
Chapter
69
H
2.4.3.3).
).
Functional Description
PEF 82912/82913
2001-03-30
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