pef82902 Infineon Technologies Corporation, pef82902 Datasheet - Page 124

• Manufacturer Part Number: pef82902
• Description: 4b3t Second Generation Modular Isdn Nt Intelligent Extended
• Manufacturer: Infineon Technologies Corporation

•
Figure 49
2.6.4
By setting the enable HDLC data bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register
the HDLC controller can access the D, B1, B2 channels or any combination of them (e.g.
18 bit IDSL data (2B+D). In all modes (except extended transparent mode) sending
works always frame aligned, i.e. it starts with the first selected channel whereas
reception looks for a flag anywhere in the serial data stream.
2.6.5
This non-HDLC mode is selected by setting MODEH.MDS2-0 to ’100’. In extended
transparent mode fully transparent data transmission/reception without HDLC framing is
performed i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing
mechanism. This allows user specific protocol variations.
Transmitter
The transmitter sends the data out of the FIFO without manipulation. Transmission is
always IOM
selected channel (B1, B2, D, according to the setting of register HCI_CR in the IOM
Handler) of the next IOM
The FIFO indications and commands are the same as in other modes.
If the microcontroller sets XTF & XME the transmitter responds with a XPR interrupt after
sending the last byte, then it returns to its idle state (sending continuous ‘1’).
If the collision detection is enabled (MODEH.DIM = ’0x1’) the stop go bit (S/G) can be
used as a clear-to-send indication as in any other mode. If the S/G bit is set to ’1’ (stop)
Data Sheet
Transmit Transparent Frame
*
1)
The CRC is generated by default.
If EXMR.XCRC is set no CRC is appended
Access to IOM
Extended Transparent Mode
(XTF)
â
-2-frame aligned and byte aligned, i.e. transmission starts in the first
Transmit Data Flow
â
-2 frame.
â
FLAG
-2 channels
ADDRESS
ADDR
110
XFIFO
CONTROL DATA
CTRL
I
Functional Description
CHECKRAM
CRC
*
1)
PEF 81902
2001-11-12
fifoflow_tran.vsd
FLAG
â
-2