lm4935rlx National Semiconductor Corporation, lm4935rlx Datasheet - Page 20
lm4935rlx
Manufacturer Part Number
lm4935rlx
Description
Audio Sub-system With Dual-mode Stereo Headphone And Mono High Efficiency Loudspeaker Amplifiers And Multi-purpose Adc
Manufacturer
National Semiconductor Corporation
Datasheet
1.LM4935RLX.pdf
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11.0 System Control
Method 2. SPI/Microwire Control/3–wire Control
The LM4935 can be controlled via a three wire interface consisting of a clock, data and an active low chip_select. To use this
control method connect SPI_MODE to BB_V
If the application requires read access to the register set; for example to determine the cause of an interrupt request or to read
back a SAR data field, the GPIO2 pin can be configured as an SPI format serial data output by setting the GPIO_SEL in the GPIO
configuration register (0x1Ah) to SPI_SDO. To perform a read rather than a write to a particular address the MSB of the register
address field is set to a 1, this effectively mirrors the contents of the register field to read-only locations above 0x80h:
(Continued)
Three Wire Mode Write Bus Timing
DD
FIGURE 3. SPI Write Transaction
FIGURE 4. SPI Read Transaction
and use TEST_MODE/CS as the chip_select as follows:
FIGURE 5. SPI Timing
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