lm49370rl National Semiconductor Corporation, lm49370rl Datasheet - Page 23

• Manufacturer Part Number: lm49370rl
• Description: Audio Sub-system With An Ultra Low Emi, Spread Spectrum, Class D Loudspeaker Amplifier, A Dual-mode Stereo Headphone Amplifier, And A Dedicated Pcm Interface For Bluetooth Transceivers
• Manufacturer: National Semiconductor Corporation

Bits
6:0
12.5 PLL M DIVIDER CONFIGURATION REGISTER
This register is used to control the input section of the PLL. (Note 12)
The M divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz.
The division of the M divider is derived from PLL_M such that:
Note 12: See Further Notes on PLL Programming for more detail.
0
7
FORCERQ
PLL_M
RSVD
Field
If set, the R and Q divider are enabled and the DAC and ADC clocks are propagated. This allows operation
of the I
a clock master.
2
S and PCM interfaces without the ADC or DAC being enabled, for example to act as a bridge or
PLL_M
126
127
TABLE 6. PLL_M (0x02h)
...
0
1
2
3
4
M = (PLL_M + 1) / 2
23
Description
RESERVED
Input Divider Value
No Divided Clock
3 to 63
63.5
1.5
2.5
64
1
2
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