el5185 Intersil Corporation, el5185 Datasheet
el5185
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el5185 Summary of contents
Page 1
... The rail-to-rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. The latch input of the EL5185 can be used to hold the comparator output value by applying a low logic level to the pin. The EL5185 is available in the 8-pin SO package and is specified for operation over the -40° ...
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... D t Minimum Setup Time S t Minimum Hold Time H t (D) Minimum Latch Disable Pulse Width PW 2 EL5185 = 25°C) Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C -) -0.2V] to [(V +) +0.2V] Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125° -0.2V] to [(V +) +0.2V] Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves S ) +0.2V] ...
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... Supply Current vs Supply Voltage 14 V =-50mV IN R =2. Offset Voltage vs Temperature 2.5 2 1.5 1 0.5 0 -0.5 -50 -30 -10 Temperature (°C) Output Low Voltage vs Temperature 0.4 0.3 0.2 0.1 -50 -30 -10 Temperature (°C) 3 EL5185 4.4 4 -50 ± ...
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... V OD Propagation Delay vs Overdrive STEP 7 6 6.6 6.4 6.2 6 5.8 0.2 0.4 0.6 0 EL5185 (Continued) Propagation Delay vs Supply Voltage 4 ± 2.3k 4.3 L 4.2 + 4.1 4 3.9 - 3.8 3.7 3.6 3.5 350 400 450 500 550 600 4 (mV) Digital Supply Current vs Switching Frequency (per comparator ± 2.3k 20 ...
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... Ambient Temperature (°C) Output with 50MHz Input P-P Output (5ns/div, 2V/div) Input (5ns/div, 2V/div) 5 EL5185 (Continued) Package Power Dissipation vs Ambient Temp. JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board 0.7 0.6 625mW 0.5 0 0.3 0.2 0 100 0 (pF) Output with 50MHz Input ...
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... Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain H unchanged in order to be acquired and held at the output t (D) Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an PW input signal change 6 EL5185 Compare Compare Latch ...
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... FUNCTION Circuit 1 (Reference Circuit 1) Circuit 2 Circuit 3 Input Voltage Considerations The EL5185 input range is specified from 0.1V below V 2.25V below V output still responds correctly to a small differential input -. The output S signal. The differential input stage is a pair of PNP transistors, therefore, the input bias current flows out of the device ...
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... Latch Pin Dynamics The EL5185 contains a transparent latch for each channel. The latch pin is designed to be driven with either a TTL or CMOS output. When the latch is connected to a logic high level or left floating, the comparator is transparent and immediately responds to the changes at the input terminals ...
Page 9
... SD DC average voltage based on the output. The crystal's path provides resonant positive feedback and stable oscillation occurs. Although the EL5185 will give the correct logic output when an input is outside the common mode range, additional delays may occur when operated. Therefore, the DC bias voltages at the inputs are set about ...