clc450 National Semiconductor Corporation, clc450 Datasheet - Page 9

• Manufacturer Part Number: clc450
• Description: Single Supply, Low-power, High Output, Current Feedback Amplifier
• Manufacturer: National Semiconductor Corporation

Transmission Line Matching
One method for matching the characteristic impedance
(Z
appropriate resistor at the input or output of the amplifier.
Figure 7 shows typical inverting and non-inverting circuit
configurations for matching transmission lines.
Non-inverting gain applications:
Inverting gain applications:
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C
greater frequency range. C
of the amplifier’s output impedance with frequency.
Power Dissipation
Follow these steps to determine the power consumption
of the CLC450:
The maximum power that the DIP, SOIC, and SOT
packages can dissipate at a given temperature is
illustrated in Figure 8. The power derating curve for
any CLC450 package can be derived by utilizing the
following equation:
where
T
V
V
JA
amb
1
2
o
) of a transmission line or cable is to place the
+
+
-
-
= Thermal resistance, from junction to ambient,
= Ambient temperature (°C)
for a given package (°C/W)
R
R
6
Connect R
Make R
Use R
loading caused by the transmission line,
or by parasitics.
Connect R
Make the resistors R
Make R
1
4
1. Calculate the quiescent (no-load) power:
2. Calculate the RMS power at the output stage:
3. Calculate the total RMS power:
Figure 7: Transmission Line Matching
to match the output transmission line over a
P
P
are the RMS voltage and current across the
external load.
P
amp
o
t
= P
3
= (V
Z
Z
0
0
1
5
to isolate the amplifier from reactive
, R
= I
II R
amp
g
3
CC
2
CC
directly to ground.
directly to ground.
, R
g
+ P
(175
- V
R
R
= Z
(V
2
5
R
R
6
3
g
, and R
load
CC
o
o
6
.
JA
) (I
compensates for the increase
- V
4
+
CLC450
-
T
, R
amb
R
load
EE
7
f
6
equal to Z
, and R
)
), where V
)
C
R
6
6
7
equal to Z
o
load
.
Z
0
and I
o
R
.
load
7
V
o
9
Layout Considerations
A proper printed circuit layout is essential for achieving
high
evaluation boards for the CLC450 (730013-DIP, 730027-
SOIC, 730068-SOT) and suggests their use as a guide
for high frequency layout and as an aid for device testing
and characterization.
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
Evaluation Board Information
Data sheets are available for the CLC730013/
CLC730027 and CLC730068 evaluation boards. The
evaluation board data sheets provide:
The CLC730013/CLC730027 data sheet also contains
tables of recommended components to evaluate several
of National’s high speed amplifiers. This table for the
CLC450 is illustrated below.
board data sheet for schematics and further information.
Components Needed to Evaluate the
CLC450 on the Evaluation Board:
frequency
Include 6.8 F tantalum and 0.1 F ceramic
Place the 6.8 F capacitors within 0.75 inches
of the power pins.
Place the 0.1 F capacitors less than 0.1 inches
from the power pins.
Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.
Minimize all trace lengths to reduce series
inductances.
Use flush-mount printed circuit board pins for
Evaluation board schematics
Evaluation board layouts
General information about the boards
R
R
capacitors on both supplies.
prototyping, never use high profile DIP sockets.
Operation section of the evaluation board data
sheet for details)
f
in
, R
, R
Figure 8: Power Derating Curves
1.0
0.8
0.6
0.4
0.2
0
g
out
-40 -20
- Use this product data sheet to select values
- Typically 50
0
Ambient Temperature ( C)
performance.
AJE
SOT
20 40 60 80 100 120
AJP
(Refer to the Basic
Refer to the evaluation
National
140 160
http://www.national.com
180
provides