clc417 National Semiconductor Corporation, clc417 Datasheet - Page 5

• Manufacturer Part Number: clc417
• Description: Dual Low-power, Programmable Gain Buffer
• Manufacturer: National Semiconductor Corporation

Channel Matching
Channel matching and crosstalk efficiency are largely
dependent on board layout. The layout of National’s dual
amplifier evaluation boards are optimized to produce
maximum channel matching and isolation. Typical
channel matching for the CLC417 is shown in Figure 3.
The CLC417’s channel-to-channel isolation is better than
70dB for input frequencies of 4MHz. Input referred
crosstalk vs. frequency is illustrated in Figure 4.
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC417 will
improve stability.
plot, in the Typical Performance section, gives the
recommended series resistance value for optimum
flatness at various capacitive loads.
Power Dissipation
The power dissipation of an amplifier can be described in
two conditions:
The following steps can be taken to determine the power
consumption for each CLC417 amplifier:
Figure 4: Input Referred Crosstalk vs. Frequency
Quiescent Power Dissipation -
P
Total Power Dissipation -
P
Q
T
-100
-120
-20
-40
-60
-80
(with Load Condition)
(No Load Condition)
1
1
Figure 3: Channel Matching
R
V
A
L
o
v
= 100
= 2V
= +2
pp
Frequency (MHz)
Frequency (MHz)
The R
10
Channel A
10
s
Channel A
Channel B
vs. Capacitive Load
Channel B
100
100
0
-90
-180
-270
-360
-450
5
Add the total RMS powers for both channels to determine
the power dissipated by the dual.
The maximum power that the package can dissipate at a
given temperature is illustrated in the Power Derating
curves in the Typical Performance section. The power
derating curve for any package can be derived by utiliz-
ing the following equation:
where: T
Layout Considerations
A proper printed circuit layout is essential for achieving
high
evaluation boards for the CLC417 (CLC730038 - DIP,
CLC730036 - SOIC) and suggests their use as a guide
for high frequency layout and as an aid for device testing
and characterization.
Supply bypassing is required for best performance. The
bypass capacitors provide a low impedance return
current path at the supply pins. They also provide high
frequency filtering on the power supply traces. Other
layout factors play a major role in high frequency
performance. The following are recommended as a basis
for high frequency layout:
Additional information is included in the evaluation board
literature.
Special Evaluation Board Considerations
To optimize off-isolation of the CLC417, cut the R
on both the 730038 and 730036 evaluation boards. This
cut minimizes capacitive feedthrough between the input
and
recommended to improve off-isolation.
1. Determine the quiescent power
2. Determine the RMS power at the output stage
3. Determine the total RMS power
1. Include 6.8 F tantalum and 0.1 F ceramic
2. Place the 6.8 F capacitors within 0.75 inches
3. Place the 0.1 F capacitors less than 0.1
4. Remove the ground plane near the input
5. Minimize all trace lengths to reduce series
output.
frequency
P
P
are the RMS voltage and current across the
external load.
P
capacitors on both supplies.
of the power pins.
inches from the power pins.
and output pins to reduce parasitic
capacitance.
inductances.
Q
O
T
JA
amb
= P
= (V
= (V
= Thermal resistance, from junction to
= Ambient temperature (°C)
ambient, for a given package (°C/W)
Q
CC
CC
Figure
+ P
P
- V
- V
O
performance.
EE
(175
load
)
5
•
) (I
I
CC
indicates
JA
load
Tamb)
), where V
National
http://www.national.com
the
load
alterations
and I
provides
f
trace
load