sae81c80a Infineon Technologies Corporation, sae81c80a Datasheet
sae81c80a
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sae81c80a Summary of contents
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CMOS Dual-Port RAM CMOS IC Features Processor interface with address and data bus plus signals ALE, WR, RD 8051-, 8096-compatible timing Memory capacity 504 bytes All functions fully static (excl. oscillator watchdog) Standby operation On-chip oscillator with separate clock output ...
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Pin Configuration (top view) Semiconductor Group 2 SAE 81C80 A ...
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Pin Definitions and Functions Pin No. Symbol Function AD10 7 8 AD11 9 AD12 10 AD13 11 AD14 12 AD15 13 AD16 14 AD17 06 A18 Address 8 port 1 37 AD20 36 AD21 35 AD22 34 AD23 33 AD24 ...
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Pin No. Symbol Function 27 RES Reset input Resets the defined initial state when RES is low. At the same time the outputs WD1, WD2, WD3 are switched low for the duration of the reset pulse. The ...
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Figure 1 Principle of the Dual-Port-RAM (DPR) Semiconductor Group 5 SAE 81C80 A ...
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Figure 2 Interfacing Master and Slave Processors by DPRs Semiconductor Group 6 SAE 81C80 A ...
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Figure 3 Dual-Port RAM used between Measured-Data Acquisition and the Actuators Functional Description Dual-Port RAM The SAE 81C80A is a 504-byte static RAM simultaneously accessible by two microcontrollers. The memory locations are selected via a multiplexed address/data bus and two ...
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Chip-Select Inputs The chip-select inputs affect signals WR and RD, but not the ALE input. Therefore, the ALE signal on the DPR (even if the DPR is not selected) must correspond to the specified values. To eliminate selection ...
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Interrupt Outputs The DPR has three interrupt outputs that can be set and reset directly by writing to an address (see table 1). The outputs are located in the same address range as the scheduling registers. However, only bits 2 ...
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Timers The three timers are 24-bit counters with a clock frequency of counters can be set by writing to three specific RAM addresses. The value is then simultaneously stored in the RAM and a buffer register of the timer. When ...
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Only for the registers of timers 1 and 2 Bit 1-3: These are used together with bit 0 for switching the watchdog mode ON and OFF. Only for the register of timer 3 Bit 1-2: Reserved (should always be 0 ...
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Figure 4 Bit Assignment of Timer-Mode Registers for Timer 1 and 2 Bit 7 Bit 6 Bit 5 Software Timer stop Mode start (= for (auto- auto- reload = 1, reload single- shot = 0) Figure 5 ...
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Access Collisions With a RAM which can be written to or read simultaneously by two controllers, different kinds of access collision are possible: 1. Simultaneous read access to the same memory location from both ports; 2. One port reads the ...
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Scheduling Registers Note: The assignment of a memory area to a scheduling register is defined by the user software of both controllers With the scheduling registers synchronization can be done with only one access because the reservation is performed during ...
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The following applies only to the scheduling registers: Usually, in the case of a concurrent access by both processors, writing has priority over reading. However, a simultaneous read or write access from the two ports means that port 1 has ...
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Notes: 1. The owner bit indicates the last owner of a register. 2. Only if the port is owner of the register will writing change the state. 3. The reset state is state 1. 4. The FSM is symmetrical. Therefore, ...
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Figure 7 Memory Map Semiconductor Group 17 SAE 81C80 A ...
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Block Diagram Semiconductor Group 18 SAE 81C80 A ...
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Absolute Maximum Ratings T = – 110 C; all voltages referred to A Parameter Storage temperature Total power dissipation Power dissipation per output Input voltage Supply voltage Operating Range Supply voltage Supply current (w/o loading of outputs) Operating ...
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DC Characteristics all voltages referred to A Parameter All Input Signals Except XTAL2 and PD H-input voltage L-input voltage Input capacitance Input current XTAL2 (as external clock input) H-input voltage L-input voltage Input capacitance PD (Schmitt-trigger ...
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AC Characteristics The AC characteristics apply throughout the operating range Parameter Read cycle time Write cycle time ALE pulse width Address setup to ALE low Address hold after ALE low RD pulse width WR pulse width ALE low to RD ...
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AC Characteristics (cont’d) The AC characteristics apply throughout the operating range Parameter Active pulse length of timer outputs Oscillator period High time Low time Pulse Diagram 1 Semiconductor Group Symbol Limit Values min ...
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Pulse Diagram 2 Note to Chip Select Timing: The shown timing is not necessary, if the device is always activated or deactivated. This means either both may be constant “high” or “low”. Semiconductor Group 23 ...
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Pulse Diagram 3 Semiconductor Group 24 SAE 81C80 A ...
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Example of Application Circuit 1) Design proposal (non-obligatory) Semiconductor Group 1) 25 SAE 81C80 A ...
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Appendix 8051 Program for Timer Operation in Watchdog Mode HBYTE EQU TMR EQU CR EQU REST1 EQU REST2 EQU WDOFF EQU ; Load reload register MOV DPTR, #HBYTE CLR A MOVX @DPTR,A DEC DPL MOV A, #0FFH MOVX @DPTR,A DEC ...
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Program for Timer Operation in Watchdog Mode (cont’d) MOV DPTR, #KR MOV A, #REST1 MOVX @DPTR,A MOV A, #WDOFF MOV DPTR, #TMR MOVX @DPTR,A MOV A, #REST2 MOV DPTR, #KR MOVX @DPTR,A ; END Semiconductor Group 27 SAE 81C80 ...