sae81c80a Infineon Technologies Corporation, sae81c80a Datasheet - Page 10

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sae81c80a

Manufacturer Part Number
sae81c80a
Description
Cmos Dual-port Ram
Manufacturer
Infineon Technologies Corporation
Datasheet

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Timers
The three timers are 24-bit counters with a clock frequency of
counters can be set by writing to three specific RAM addresses. The value is then
simultaneously stored in the RAM and a buffer register of the timer. When the low byte
is written, all three bytes are parallely stored in the reload register. The value in the
reload register is kept in all operating modes until the associated low byte is written
again.
The counters are down-counters. They can be started by setting bit 7 in the associated
timer-mode register (TMR). Each counter can be configured by a TMR. The bits of the
TMRs have the following function:
Bit 0:
Bit 4:
Bit 5:
Bit 6:
Bit 7:
Semiconductor Group
This bit provides overwrite protection for the reload register.
Use: After writing to the reload registers and starting of the timer – by writing to
the associated protection bit – the adjacent RAM area can be used without
affecting the reload register (reset state = 0).
It serves for switching the polarity of the output signal (reset state = 0).
Bit 4 = 0; idle state 1, active 0
Bit 4 = 1; idle state 0, active 1
This bit switches the operating mode (reset state = 0).
Bit 5 = 0 single-shot, i.e. when the counter is started, the output signal
becomes active. After reaching zero, the output signal is reset. The timer has to
be restarted to trigger another count cycle. The values from the reload register
are then loaded into the counter.
Bit 5 = 1 auto reload, i.e. when the counter is started, the value of the reload
register is loaded into it. When zero is reached, the counter issues a pulse
( 4 s at 12 MHz), automatically reloads the original value and the entire
operation starts again. In this way a frequency can be set with a resolution of
24 bits. Because of the pulse width of eight timer clock pulses, however, the
shortest period is limited to nine timer clock pulses (
appears in the count cycle (even without “STOP”), no pulse is issued and the
counter is reloaded.
In the reload mode the timer can be halted by setting this bit and resetting bit 5.
(In a new start the contents of the counter are lost and that of the reload
registers remain unaffected).
Setting this bit starts the counter.
10
t
osx
6). If a new start pulse
f
OSC
/6. Each of the
SAE 81C80 A

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