z89176 ZiLOG Semiconductor, z89176 Datasheet - Page 23
z89176
Manufacturer Part Number
z89176
Description
Voice Processing Controllers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z89176.pdf
(68 pages)
- Current page: 23 of 68
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Zilog
For external memory references, Port 0 provides address
bits A11-A8 (lower nibble) or A15-A8 (lower and upper nib-
ble) depending on the required address space. If the ad-
dress range requires 12 bits or less, the upper nibble of
Port 0 can be programmed independently as I/O while the
lower nibble is used for addressing. If one or both nibbles
are needed for I/O operation, they are configured by writ-
ing to the Port 0 mode register.
DS97TAD0100
OEN
Out
In
1.5
Z89175/176
MCU
2.3V Hysteresis
Figure 11. Port 0 Configuration
P R E L I M I N A R Y
R = 500 K
4
4
In ROMless mode, after a hardware reset, Port 0 is config-
ured as address lines A15-A8, and extended timing is set
to accommodate slow memory access. The initialization
routine can include reconfiguration to eliminate this ex-
tended timing mode. (In ROM mode, Port 0 is defined as
input after reset.)
Port 0 is set in the high-impedance mode if selected as an
address output state along with Port 1 and the control sig-
nals /AS, /DS, and R//W (Figure 11).
Port 0
(I/O or A15 - A8)
Handshake Controls
/DAV0 and RDY0
(P32 and P35)
Voice Processing Controllers
Auto Latch
Z89175/Z89176
Pad
23
2
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