adcmp572 Analog Devices, Inc., adcmp572 Datasheet - Page 9

• Manufacturer Part Number: adcmp572
• Description: Ultrafast 3.3 V/5 V Single-supply Comparators
• Manufacturer: Analog Devices, Inc.

APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP572/ADCMP573 comparators are very high speed
SiGe devices. Consequently, it is essential to use proper high
speed design techniques to achieve the specified performance.
Of critical importance is the use of low impedance supply
planes, particularly the output supply plane (V
ground plane (GND). Individual supply planes are recom-
mended as part of a multilayer board. Providing the lowest
inductance return path for switching currents ensures the best
possible performance in the target application.
It is important to adequately bypass the input and output
supplies. A 1 µF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.01 µF bypass capacitors should
be placed as close as possible to each of the V
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be avoided to maximize the
effectiveness of the bypass at high frequencies.
If the input and output supplies are connected separately such
that V
supplies separately to the GND plane. A bypass capacitor should
not be connected between them. It is recommended that the
GND plane separate the V
board layout is designed to minimize coupling between the two
supplies and to take advantage of the additional bypass capaci-
tance from each respective supply to the ground plane. This
enhances the performance when split input/output supplies are
used. If the input and output supplies are connected together for
single-supply operation such that V
the two supplies is unavoidable; however, every effort should be
made to keep the supply plane adjacent to the GND plane to
maximize the additional bypass capacitance this arrangement
provides.
CML/RSPECL OUTPUT STAGE
Specified propagation delay dispersion performance can be
achieved only by using proper transmission line terminations.
The outputs of the ADCMP572 are designed to directly drive
400 mV into 50 Ω cable, microstrip, or strip line transmission
lines properly terminated to the V
output stage is shown in the simplified schematic diagram of
Figure 15. The outputs are each back terminated with 50 Ω for
best transmission line matching. The RSPECL outputs of the
ADCMP573 are illustrated in Figure 16 and should be
terminated to V
termination networks can be used in either case if the direct
termination voltage is not readily available. If high speed output
signals must be routed more than a centimeter, microstrip or
CCI
≠ V
CCO
, care should be taken to bypass each of these
CCO
− 2 V. As an alternative, Thevenin equivalent
CCI
and V
CCO
CCO
CCI
supply plane. The CML
= V
planes when the circuit
CCO
CCI
, coupling between
CCO
and V
) and the
CCO
Rev. 0 | Page 9 of 16
strip line techniques are essential to ensure proper transition
times and to prevent output ringing and pulse width dependent
propagation delay dispersion. For the most timing critical
applications where transmission line reflections pose the
greatest risk to performance, the ADCMP572 provides the best
match to 50 Ω output transmission paths.
USING/DISABLING THE LATCH FEATURE
The latch inputs (LE/ LE ) are active low for latch mode and are
internally terminated with 50 Ω resistors to Pin 8. This pin
corresponds to and is internally connected to the V
for the CML-compatible ADCMP572. With the aid of these
resistors the ADCMP572 latch function can be disabled by
connecting the LE pin to GND with an external pull-down
resistor and leaving the LE pin unconnected. To avoid excessive
power dissipation, the resistor should be 750 Ω when V
3.3 V, and 1.2 kΩ when V
ADCMP573, the V
PECL termination supply at V
disabled by connecting the LE pin to V
Figure 15. Simplified Schematic Diagram of
Figure 16. Simplified Schematic Diagram of
the ADCMP573 RSPECL Output Stage
the ADCMP572 CML Output Stage
TT
pin should be connected externally to the
GND
CCO
16mA
ADCMP572/ADCMP573
= 5.2 V. In the PECL-compatible
V
V
GND
CCO
CCO
CCO
– 2 V. The latch can then be
50Ω
CCO
Q
Q
with an external
Q
Q
CCO
supply
CCO
=