pnx8511 NXP Semiconductors, pnx8511 Datasheet - Page 23

• Manufacturer Part Number: pnx8511
• Description: Analog Companion Chip
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12612
Product data
7.1.11 Macrovision™ - PNX8510
7.2 HD data path
The encoder supports Macrovision¥ Anti-Taping for both NTSC and PAL. There is no
Macrovision™ insertion for SECAM defined, however for AGC Pseudo Sync and BP
pulses the same settings used for PAL could be used for SECAM. The different steps
of this process can be programmed separately. The Macrovision™ control block
provides all necessary timing and level information for inserting the correct pulses in
the CVBS/Y/C/RGB/YUV data stream. Furthermore it provides the signals used to
modify the subcarrier generator according to the Macrovision™ Burst Inversion
requirements.
The encoder uses a blanking level during the vertical blanking interval that is defined
by the value of BLNVB, thus providing two different programmable blanking levels.
Outside vertical blanking, value of BLNNL is effective, which should be reduced
according to Macrovision™ requirements. The copy protection means can be
activated independently by the respective control bits. The Macrovision™ registers
and definition of each of these registers are defined in a separate Macrovision™
Supplement document.
Remark: Macrovision™ is not available in PNX8511.
The high definition data path of the PNX8510/11 IC features an up-sampling filter,
gain control and a universal sync insertion engine.
Input formats supported by the high definition data path are:
RGB and YUV data types are accepted. However, there is no color space conversion
in the HD data path so the input data type has to match the display data type.
The up-sampling filter can be applied to convert incoming 422 data formats to 444.
The data path also provides individual gain control for RGB/YUV which allows a 
+/-0.5x amplitude change (HD_GAIN_RY, HD_GAIN_GU, HD_GAIN_BV control
registers).
The HD sync insertion module following the filter and gain control circuits provides
flexible insertion of synchronization signals into the Y, Y and V or R, G and B data
paths. The insertion can be chosen on a component basis (Y/R_SYNC_INS_EN,
U/G_SYNC_INS_EN, V/B_SYNC_INS_EN control registers) and the sync generator
provides individual tables for the components. A more detailed description of the sync
generator can be found in the next paragraph.
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Double D1 mode:16/20 bit 422 (8/10 bit for Y and 8/10 bit for U/V);
DEMUX_MODE of Register VMUXCTL, offset 0x95 is set to 3’b011
Single interface HD 422 mode (UYVY 422 D1 format); DEMUX_MODE of Register
VMUXCTL, offset 0x95 is set to 3’b100
Single interface 444 (RGB/YUV 444 format); DEMUX_MODE of Register
VMUXCTL, offset 0x95 is set to 3’b001
Full 24/30 bit parallel input mode (YUV/RGB 444 formats); VMODE of Register
MISCCTRL, offset 0xA5 is set to zero
Rev. 04 – 12 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
PNX8510/11
Analog companion chip
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