m35080-mn6t STMicroelectronics, m35080-mn6t Datasheet - Page 7

• Manufacturer Part Number: m35080-mn6t
• Description: 8 Kbit Serial Spi Bus Eeprom With Incremental Registers
• Manufacturer: STMicroelectronics

Table 7. Write Protected Block Size
Note: 1. Except for the first sixteen pairs of bytes (see Table 6).
Software Protected Mode (SPM)
The act of writing a non-zero value to the BP1 and
BP0 bits causes the Software Protected Mode
(SPM) to be started. All attempts to write a byte or
page in the protected area are ignored, even if the
Write Enable Latch is set. However, writing is still
allowed in the unprotected area of the memory ar-
ray and to the SRWD, BP1 and BP0 bits of the sta-
tus register, provided that the WEL bit is first set.
Hardware Protected Mode (HPM)
The Hardware Protected Mode (HPM) offers a
higher level of protection, and can be selected by
setting the SRWD bit after pulling down the W pin
or by pulling down the W pin after setting the
SRWD bit. The SRWD is set by the WSR instruc-
tion, provided that the WEL bit is first set. The set-
ting of the SRWD bit can be made independently
of, or at the same time as, writing a new value to
the BP1 and BP0 bits.
Once the device is in the Hardware Protected
Mode, the data bytes in the protected area of the
memory array, and the content of the status regis-
ter, are write-protected. The only way to re-enable
writing new values to the status register is to pull
the W pin high. This cause the device to leave the
Hardware Protected Mode, and to revert to being
in the Software Protected Mode. (The value in the
BP1 and BP0 bits will not have been changed).
Further details of the operation of the Write Protect
pin (W) are given earlier, on page 2.
Typical Use of HPM and SPM
The W pin can be dynamically driven by an output
port of a microcontroller. It is also possible,
though, to connect it permanently to V
der connection, or through a pull-down resistor).
The manufacturer of such a printed circuit board
can take the memory device, still in its initial deliv-
ery state, and can solder it directly on to the board.
After power on, the microcontroller can be instruct-
ed to write the protected data into the appropriate
area of the memory. When it has finished, the ap-
propriate values are written to the BP1, BP0 and
SRWD bits, thereby putting the device in the hard-
ware protected mode.
BP1
0
0
1
Status Register Bits
BP0
0
1
0
SS
(by a sol-
Protected Block
Upper quarter
Upper half
none
An alternative method is to write the protected da-
ta, and to set the BP1, BP0 and SRWD bits, before
soldering the memory device to the board. Again,
this results in the memory device being placed in
its hardware protected mode.
If the W pin has been connected to V
down resistor, the memory device can be taken
out of the hardware protected mode by driving the
W pin high, to override the pull-down resistor.
If the W pin has been directly soldered to V
there is only one way of taking the memory device
out of the hardware protected mode: the memory
device must be de-soldered from the board, and
connected to external equipment in which the W
pin is allowed to be taken high.
Read Operation
The chip is first selected by holding S low. The se-
rial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in
during the rising edge of the clock (C). The data
stored in the memory, at the selected address, is
shifted out on the Q output pin. Each bit is shifted
out during the falling edge of the clock (C) as
shown in Figure 5.
The internal address counter is automatically in-
cremented to the next higher address after each
byte of data has been shifted out. The data stored
in the memory, at the next address, can be read by
successive clock pulses. When the highest ad-
dress is reached, the address counter rolls over to
“0000h”, allowing the read cycle to be continued
indefinitely. The read operation is terminated by
deselecting the chip. The chip can be deselected
at any time during data output. If a read instruction
is received during a write cycle, it is rejected, and
the memory device deselects itself.
Byte Write Operation
Before any write can take place, the WEL bit must
be set, using the WREN instruction, as shown in
Figure 8. The write state is entered by selecting
the chip, issuing three bytes of instruction and ad-
dress, and one byte of data. Chip Select (S) must
remain low throughout the operation, as shown in
Figure 9. The device must be deselected just after
the eighth bit of the data byte has been latched in,
1
Array Addresses Protected
0300h - 03FFh
0200h - 03FFh
M35080
none
1
SS
M35080
by a pull-
7/18
SS
,