74aup1g18gw NXP Semiconductors, 74aup1g18gw Datasheet

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74aup1g18gw

Manufacturer Part Number
74aup1g18gw
Description
74aup1g18 Low-power 1-of-2 Demultiplexer With 3-state Deselected Output
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
74aup1g18gw,125
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. General description
2. Features
The 74AUP1G18 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
static and dynamic power consumption across the entire V
This device is fully specified for partial Power-down applications using I
The I
the device when it is powered down.
The 74AUP1G18 provides a 1-of-2 non-inverting demultiplexer with 3-state output. The
74AUP1G18 buffers the data on input pin (A) and passes it either to output 1Y or 2Y,
depending on whether the state of the select input pin (S) is LOW or HIGH.
I
I
I
I
I
I
I
I
I
I
I
74AUP1G18
Low-power 1-of-2 demultiplexer with 3-state deselected
output
Rev. 01 — 13 October 2006
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
N
N
N
N
N
N
N
N
OFF
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114-D Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101-C exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
range from 0.8 V to 3.6 V. This device ensures a very low
CC
= 0.9 A (maximum)
CC
CC
range from 0.8 V to 3.6 V.
Product data sheet
OFF
.

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74aup1g18gw Summary of contents

Page 1

Low-power 1-of-2 demultiplexer with 3-state deselected output Rev. 01 — 13 October 2006 1. General description The 74AUP1G18 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all ...

Page 2

... Temperature range Name 74AUP1G18GW +125 C 74AUP1G18GM +125 C 74AUP1G18GF +125 C 4. Marking Table 2. Marking Type number 74AUP1G18GW 74AUP1G18GM 74AUP1G18GF 5. Functional diagram Fig 1. Logic symbol 74AUP1G18_1 Product data sheet Low-power 1-of-2 demultiplexer with 3-state deselected output Description SC-88 plastic surface-mounted package; 6 leads XSON6 plastic extremely thin small outline package ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP1G18 GND 001aae822 Fig 2. Pin configuration SOT363 (SC-88) 6.2 Pin description Table 3. Pin description Symbol Pin S 1 GND Functional description [1] Table 4. Function table Input ...

Page 4

... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current output voltage O I output current ...

Page 5

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I OFF-state output current ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter +85 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I OFF-state output current ...

Page 7

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter +125 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I OFF-state output current ...

Page 8

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay A to nY; see enable time S to nY; see disable time S to nY; see ...

Page 9

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t enable time S to nY; see disable time S to nY; see dis propagation delay A to nY; see ...

Page 10

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay A to nY; see enable time S to nY; see disable time S to nY; see dis ...

Page 11

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions pF and power dissipation MHz capacitance V = GND [1] All typical values are measured at nominal V ...

Page 12

... NXP Semiconductors S input nY output LOW-to-OFF OFF-to-LOW nY output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Logic levels: V and V are typical output voltage drop that occur with the output load Fig 6. Enable and disable times Table 10. Measurement points Supply voltage ...

Page 13

... NXP Semiconductors Test data is given in Table 11. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 7. Load circuitry for switching times Table 11 ...

Page 14

... NXP Semiconductors 13. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 0.30 1.1 0.25 mm 0.1 0.20 0.8 0.10 OUTLINE VERSION IEC SOT363 Fig 8. Package outline SOT363 (SC-88) 74AUP1G18_1 Product data sheet Low-power 1-of-2 demultiplexer with 3-state deselected output ...

Page 15

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION ...

Page 16

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 OUTLINE VERSION IEC SOT891 Fig 10. Package outline SOT891 (XSON6) 74AUP1G18_1 Product data sheet ...

Page 17

... NXP Semiconductors 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 13. Revision history Document ID Release date 74AUP1G18_1 ...

Page 18

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 19

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Abbreviations ...

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