sstvf16859bs NXP Semiconductors, sstvf16859bs Datasheet

sstvf16859bs

Manufacturer Part Number

sstvf16859bs

Description

13-bit 1 2 Sstl_2 Registered Buffer For Ddr

Manufacturer

NXP Semiconductors

Datasheet

1.SSTVF16859BS.pdf (23 pages)

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

SSTVF16859BS

Manufacturer:

NXP

Quantity:

12 000

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1. General description

The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock

inputs, designed to operate between 2.3 V and 2.7 V for PC1600-PC2700 applications or

between 2.5 V and 2.7 V for PC3200 applications. All inputs are compatible with the

JEDEC standard for SSTL_2 with V

(RESET) input. All outputs are SSTL_2, Class II compatible, which can be used for

standard stub-series applications or capacitive loads. Master reset (RESET)

asynchronously resets all registers to zero.

The SSTVF16859 is intended to be incorporated into standard DIMM (Dual In-Line

Memory Module) designs deﬁned by JEDEC, such as DDR (Double Data Rate) SDRAM

and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM

transfers data on both clock edges (rising and falling), thus doubling the peak bus

bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz.

The device data inputs consist of different receivers. One differential input is tied to the

input pin while the other is tied to a reference input pad, which is shared by all inputs.

The clock input is fully differential (CK and CK) to be compatible with DRAM devices that

are installed on the DIMM. Data are registered at the crossing of CK going HIGH, and CK

going LOW. However, since the control inputs to the SDRAM change at only half the data

rate, the device must only change state on the positive transition of the CK signal. In order

to be able to provide deﬁned outputs from the device even before a stable clock has been

supplied, the device has an asynchronous input pin (RESET), which when held to the

LOW state, resets all registers and all outputs to the LOW state.

The device supports low-power standby operation. When RESET is LOW, the differential

input receivers are disabled, and un-driven (ﬂoating) data, clock, and reference voltage

(VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and

all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid

logic HIGH or LOW level.

To ensure deﬁned outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR DIMM application, RESET is speciﬁed to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering RESET, the register will be cleared and the outputs will be driven

LOW. As long as the data inputs are LOW, and the clock is stable during the time from the

LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the outputs

will remain LOW.

SSTVF16859

13-bit 1 : 2 SSTL_2 registered buffer for DDR

Rev. 02 — 19 July 2005

ref

normally at 0.5

Product data sheet

, except the LVCMOS reset

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