at24c04c-xhm-t ATMEL Corporation, at24c04c-xhm-t Datasheet - Page 9

• Manufacturer Part Number: at24c04c-xhm-t
• Description: I 2 C-compatible 2-wire Serial Eeprom
• Manufacturer: ATMEL Corporation

8787A–SEEPR–10/11
6.
7.
Device Addressing
STANDARD EEPROM ACCESS: The 4K and 8K EEPROM device requires an 8-bit device address word following
a start condition to enable the chip for a read or write operation. The device address word consists of a mandatory
‘1010’ (0xA) sequence for the first four most significant bits as shownin
all the EEPROM devices.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit.
The two device address bits must compare to their corresponding hard-wired input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with the next two bits being for memory page addressing.
The A2 must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is
high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will
return to a standby state.
For the SOT23 package offering, the 4K EEPROM software A2 and A1 bits in the device address word must be set
to zero to properly communicate. The 8K EEPROM software A2 bit in the device address word must be set to zero
to properly communicate.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the
first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the
EEPROM enters an internally timed write cycle, t
write cycle and the EEPROM will not respond until the write is complete (see
PAGE WRITE: The 4K and 8K EEPROM is capable of a 16-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the
microcontroller can transmit up to seven data words. The EEPROM will respond with a zero after each data word
received. The microcontroller must terminate the page write sequence with a stop condition (see
page
The data word address lower three bits are internally incremented following the receipt of each data word. The
higher data word address bits are not incremented, retaining the memory page row location. When the word
address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the
same page. If more than eight data words are transmitted to the EEPROM, the data word address will “roll over”
and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are
disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device
address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a zero allowing the read or write sequence to continue.
11).
WR
, to the nonvolatile memory. All inputs are disabled during this
Atmel AT24C04C/08C [PRELIMINARY]
Figure 8-1 on page
Figure 8-2 on page
10. This is common to
10).
Figure 8-3 on
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