at25dq321a ATMEL Corporation, at25dq321a Datasheet
at25dq321a
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at25dq321a Summary of contents
Page 1
... Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (150-mil and 208-mil wide) – 16-lead SOIC (300-mil wide) – 8-pad Very Thin DFN ( 0.6 mm) 32-Megabit 2.7-volt Minimum SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support AT25DQ321A Preliminary 8718A–DFLASH–04/10 ...
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... Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The physical sectoring and the erase block sizes of the AT25DQ321A have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently ...
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... Dual-Output and Quad-Output Read Array commands in which it will be referenced as I/O The SO pin will high-impedance state whenever the device is deselected (CS is deasserted). 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] ): The SI pin is used to shift data into the device. The conjunction with other pins to allow two bits (on 0 ...
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... WP (I/O ) SCK GND SI (I AT25DQ321A [Preliminary The WP# pin controls the hardware locking feature and, along with other pins, allows four bits (on I data to be clocked out on every falling edge of 3-0 See “Hold” on page 49. for additional details on the ) and, along with other pins, allows four bits (on I/O ...
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... Memory Array To provide the greatest flexibility, the memory array of the AT25DQ321A can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations. The size of the physical sectors is optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions ...
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... Sector Protection Block Erase Function (D8h Command) (52h Command) 64KB 64KB (Sector 63) 64KB 64KB (Sector 62) 64KB 64KB (Sector 0) AT25DQ321A [Preliminary] 6 Block Erase Detail 32KB 4KB Block Address Block Erase Block Erase Range (20h Command) 3FFFFFh – 3FF000h 4KB 4KB 3FEFFFh – 3FE000h 4KB 3FDFFFh – ...
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... Device Operation The AT25DQ321A is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25DQ321A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). ...
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... All opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25DQ321A will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted) ...
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... Read Array operation. If the 1Bh opcode is used, then two dummy bytes must be clocked into the device after the three address bytes. If the 0Bh opcode is used, then a single dummy byte must be clocked in after the address bytes. 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] Opcode Frequency 3Ch ...
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... Figure 7-1. Read Array – 1Bh Opcode CS SCK SI SO Figure 7-2. Read Array – 0Bh Opcode CS SCK SI SO Figure 7-3. Read Array – 03h Opcode CS SCK SI SO AT25DQ321A [Preliminary] 10 8718A–DFLASH–04/10 ...
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... During the first clock cycle, bit 7 of the first data byte will be output on the I and I/O pins, respectively. The sequence continues with each byte of data 1 0 AT25DQ321A [Preliminary] pin. During the next clock cycle, bits 5 and 4 of the first pins into a high-impedance state. The 1-0 . RDDO pin ...
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... In this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the AT25DQ321A [Preliminary] 12 pins. The data is always output with the MSB of a byte first, and the MSB is always ...
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... If a programming error arises, it will be indicated by the EPE bit in the Status Register. Figure 8-1. Byte Program CS SCK SI SO 8718A–DFLASH–04/10 AT25DQ321A [Preliminary only programming a single byte “Sector Lockdown” on page 31), then the Byte/Page Program command will not “Protect Sector” ...
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... The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the AT25DQ321A [Preliminary] 14 “Write Enable” on page ...
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... If a programming error arises, it will be indicated by the EPE bit in the Status Register. Figure 8-3. Dual-Input Byte Program CS SCK Figure 8-4. Dual-Input Page Program CS SCK 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] “Sector Lockdown” on page 31), then the Byte/Page Program command will not “Protect Sector” time ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly programming error arises, it will be indicated by the EPE bit in the Status Register. AT25DQ321A [Preliminary] 16 (See “Write Enable” on page pins ...
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... MSB OPCODE ADDRESS BITS A23- MSB AT25DQ321A [Preliminary BYTE MSB BYTE 1 BYTE 2 BYTE 3 ...
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... Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-7. Block Erase CS SCK SI SO AT25DQ321A [Preliminary BLKE 8718A–DFLASH–04/10 ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-8. Chip Erase CS SCK SI SO 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] . CHPE 19 ...
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... However Reset is performed while a sector is program suspended, the suspend operation will abort but only the contents of the page that was being programmed and subsequently suspended will be undefined. The remaining pages in the 64-Kbyte sector will retain their previous contents. AT25DQ321A [Preliminary The Program Suspend (PS) bit or the Erase Suspend (ES) bit in the Status SUSP “ ...
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... Write Status Register (All Opcodes) Read Configuration Register Write Configuration Register Miscellaneous Commands Reset Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] Operation During Operation During Program Suspend Erase Suspend Allowed Not Allowed Not Allowed Not Allowed ...
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... RDY/BSY bit or the appropriate bit in the Status Register to determine if the previously suspended program or erase operation has resumed. Figure 8-10. Program/Erase Resume CS SCK SI SO AT25DQ321A [Preliminary] 22 time before issuing the Program/Erase Suspend RES 8718A–DFLASH–04/10 ...
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... CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. Write Enable CS SCK SI SO 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] 23 ...
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... CS pin is deasserted, and the CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-2. Write Disable CS SCK SI SO AT25DQ321A [Preliminary] 24 8718A–DFLASH–04/10 ...
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... Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-3. Protect Sector CS SCK SI SO 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] 25 ...
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... Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-4. Unprotect Sector CS SCK SI SO AT25DQ321A [Preliminary] 26 Table 9-1 for Sector Protection Register values). Every physical 8718A–DFLASH–04/10 ...
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... Flash memory array will not change, and WEL bit in the Status Register will be reset back to a logical “0”. 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] Table 9-2 details the conditions necessary for a Global Protect or Global Unprotect “Write Status Register Byte 1” on page 40 ...
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... Status Register to change the SPRL bit from a logical “1” logical “0” provided the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from AT25DQ321A [Preliminary] 28 Bit Protection Operation Global Unprotect – ...
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... Status Register can be read to determine if all, some, or none of the sectors are software protected (refer to Status Register” on page 36 Figure 9-5. Read Sector Protection Register CS SCK SI SO 8718A–DFLASH–04/10 and Table 11-1 on page 36 , the first byte of data output will not be valid. Therefore, if operating at clock CLK for more details). AT25DQ321A [Preliminary] for details on the Status Register “Read 29 ...
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... Hardware 0 1 Locked 1 0 Software 1 1 Locked AT25DQ321A [Preliminary] 30 Sector Protection Register ( SPRL Change Allowed Sector Protection Registers Can be modified Unlocked and modifiable using the Protect and Unprotect Sector from commands. Global Protect and Unprotect can also be performed. ...
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... WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] 41). To issue the Sector Lockdown command, the below). If the Sector Lockdown command is disabled or if the sector lockdown ...
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... When the device aborts the Freeze Sector Lockdown State operation, the WEL bit in the Status Register will be reset to a logical “0”; however, the state of the SLE bit will be unchanged. Figure 10-2. Freeze Sector Lockdown State CS SCK SI SO AT25DQ321A [Preliminary addition, the WEL bit in the Status LOCK 8718A–DFLASH–04/10 ...
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... The remaining 64 bytes of the OTP Security Register (byte locations 64 through 127) are factory programmed by Atmel and will contain a unique value for each device. The factory programmed data is fixed and cannot be changed. 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] , the first byte of data output will not be valid. Therefore, if operating at clock CLK 33 ...
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... For faster throughput recommended that the Status Register be polled rather than waiting the t time to determine if the data bytes have finished programming. At some point before the OTP Security OTPP Register programming completes, the WEL bit in the Status Register will be reset back to the logical “0” state. AT25DQ321A [Preliminary] 34 Security Register Byte Number 62 ...
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... Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 10-5. Read OTP Security Register CS SCK SI SO 8718A–DFLASH–04/10 AT25DQ321A [Preliminary read the OTP Security Register, the CS pin must first be asserted MAX 35 ...
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... Notes: 1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register Byte 1 command. 2. R/W = Readable and writeable R = Readable only AT25DQ321A [Preliminary the first two bytes of data output from the Status Register will not be valid. CLK , at least four bytes of data must be clocked out from the ...
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... Protection Registers are locked). In order to reset the SPRL bit back to a logical “0” using the Write Status Register Byte 1 command, the WP pin will have to first be deasserted. The SPRL bit is the only bit of Status Register Byte 1 that can be user modified via the Write Status Register Byte 1 command. 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] (2) Type Description R 0 Reserved for future use ...
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... Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, Write Status Register, or Write Configuration Register command must have been clocked into the device. AT25DQ321A [Preliminary] 38 8718A–DFLASH–04/10 ...
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... To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” logical “0”. Figure 11-1. Read Status Register CS SCK SI SO 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] 39 ...
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... Write Status Register Byte 1 Format Bit 7 Bit 6 SPRL X Figure 11-2. Write Status Register Byte 1 CS SCK SI SO AT25DQ321A [Preliminary] 40 Table 11-3). Any additional data bytes that are sent to the device will be ignored. Bit 5 Bit 4 Bit 3 Global Protect/Unprotect “Global Protect/Unprotect” on page 27 Bit 2 Bit 1 ...
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... Table 11-4. Write Status Register Byte 2 Format Bit 7 Bit Figure 11-3. Write Status Register Byte 2 CS SCK SI SO 8718A–DFLASH–04/10 Bit 5 Bit 4 Bit 3 X RSTE SLE AT25DQ321A [Preliminary] Table 11-4). Any additional data bytes Bit 2 Bit 1 Bit ...
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... The unwanted device operation. The Reset command has no effect on the QE bit. The QE bit defaults to the logical “0” state when devices are initially shipped from Atmel. AT25DQ321A [Preliminary the first byte of data output will not be valid. Therefore, if operating at clock CLK ...
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... CONFIGURATION REGISTER OUT MSB 11-6). Any additional data clocked into the device will be ignored. When the CS pin is Bit 5 Bit 4 Bit AT25DQ321A [Preliminary CONFIGURATION REGISTER OUT MSB ...
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... The remaining pages in the 64-Kbyte sector will retain their previous contents. The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, no Reset operation will be performed. AT25DQ321A [Preliminary ...
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... Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] . Since not all CLK 45 ...
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... Sub Code Device ID (Part 2) 0 Table 12-3. Byte Number Bit 7 Bit 6 RFU Figure 12-2. Read Manufacturer and Device SCK OPCODE SI 9Fh HIGH-IMPEDANCE SO Note: Each transition AT25DQ321A [Preliminary] 46 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 JEDEC Assigned Code Density Code ...
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... The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. Figure 12-3. Deep Power-Down CS SCK 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] 47 ...
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... If the complete opcode is not clocked in before the CS pin is deasserted the CS pin is not deasserted on a byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down mode. Figure 12-4. Resume from Deep Power-Down CS SCK AT25DQ321A [Preliminary] 48 and return to RDPD 8718A–DFLASH–04/10 ...
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... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. Figure 12-5. Hold Mode CS SCK HOLD 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] 49 ...
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... I Active Current, Erase Operation CC3 I Input Leakage Current LI AT25DQ321A [Preliminary] 50 *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these ratings or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Maximum Clock Frequency for 6Bh Opcode (Quad-Output Read) RDQO 8718A–DFLASH–04/10 Condition V = CMOS levels OUT I = 1.6 mA Min -100 µ Min OH CC Maximum Clock Frequencies – AT25DQ321A [Preliminary] Min Typ 0 0 0.2V CC Min Max Units 1 µ 0 Max ...
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... Chip Select High to Standby Mode RDPD t Reset Time RST Note: 1. Not 100% tested (value guaranteed by design and characterization load at frequencies above 70 MHz otherwise. 3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1. AT25DQ321A [Preliminary] 52 Min Max Units 4.3 ns 4.3 ns ...
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... R F 13.9 Output Test Load DEVICE UNDER TEST 15 pF (frequencies above 70 MHz) or 30pF 8718A–DFLASH–04/10 to Chip Select Low Time AC MEASUREMENT LEVEL AT25DQ321A [Preliminary] Min Typ 1 Kbytes 50 32 Kbytes 250 64 Kbytes 400 36 Program 10 Erase 25 Program 10 Erase 12 ...
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... AC Waveforms Figure 14-1. Serial Input Timing CS SCK SI SO Figure 14-2. Serial Output Timing CS SCK SI SO Figure 14-3. WP Timing for Write Status Register Byte 1 Command When SPRL = SCK SI SO AT25DQ321A [Preliminary] 54 8718A–DFLASH–04/10 ...
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... Figure 14-4. HOLD Timing – Serial Input CS SCK HOLD SI SO Figure 14-5. HOLD Timing – Serial Output CS SCK HOLD SI SO 8718A–DFLASH–04/10 AT25DQ321A [Preliminary] 55 ...
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... Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 16S 16-lead, 0.300” Wide, Plastic Gull Wing Small Outline Package (SOIC) AT25DQ321A [Preliminary Package Lead (Pad) Finish ...
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... E E2 Option A 1 Pin #1 Notch (0.20 R) (Option TITLE 8MA1, 8-pad ( 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) AT25DQ321A [Preliminary] C Side View Pin #1 Chamfer (C 0.35) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM A 0.45 0. ...
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... GND SDA SCL Top View e Side View Notes: 1. These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. Package Drawing Contact: packagedrawings@atmel.com AT25DQ321A [Preliminary TITLE 8S1, 8-lead, (0.150” ...
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... L is the length of the terminal for soldering to a substrate. Package Drawing Contact: packagedrawings@atmel.com 8718A–DFLASH–04/ Top View e D Side View TITLE 16S, 16-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) AT25DQ321A [Preliminary COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM A 2.35 – A1 0.10 – ...
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... Revision History Doc. Rev. Date 8718A 4/2010 AT25DQ321A [Preliminary] 60 Comments Initial document release 8718A–DFLASH–04/10 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Atmel Europe Unit 1-5 & ...