at25128b ATMEL Corporation, at25128b Datasheet - Page 9

• Manufacturer Part Number: at25128b
• Description: Spi Serial Eeproms
• Manufacturer: ATMEL Corporation

8593A–SEEPR–01/09
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection.
The AT25128B/256B is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory
segments can be protected. Any of the data within any selected segment will therefore be read only. The block write
protection levels and corresponding status register control bits are shown in
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular
memory cells (e.g. WREN, t
Table 8.
The WRSR instruction also allows the user to enable or disable the write protect (
protect enable (WPEN) bit. Hardware write protection is enabled when the
Hardware write protection is disabled when either the
hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the
blockprotected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are
not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the
Table 9.
READ SEQUENCE (READ): Reading the AT25128B/256B via the SO pin requires the following sequence. After the
WRITE SEQUENCE (WRITE): In order to program the AT25128B/256B, two separate instructions must be executed.
0
1 (1/4)
2 (1/2)
3 (All)
Level
WPEN
held low.
X
X
0
0
1
1
Block Write Protect Bits
WPEN Operation
byte address to be read
ignored. The data (D7 - D0) at the specified address is then shifted out onto the SO line. If only one
byte is to be read, the
can be continued since the byte address is automatically incremented and data will continue to be
shifted out. When the highest address is reached, the address counter will roll over to the lowest
address allowing the entire memory to be read in one continuous read cycle.
First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write
instruction may be executed. Also, the address of the memory location(s) to be programmed must be
outside the protected address field location selected by the Block Write Protection Level. During an
internal write cycle, all commands will be ignored except the RDSR instruction.
BP1
Status Register Bits
0
0
1
1
line is pulled low to select a device, the Read op-code is transmitted via the SI line followed by the
High
High
Low
Low
WC
X
X
, RDSR).
BP0
0
1
1
0
(Table 10
line should be driven high after the data comes out. The read sequence
WEN
0
1
0
1
0
1
3000 – 3FFF
2000 – 3FFF
0000 – 3FFF
on
AT25128B
Array Addresses Protected
page
None
Protected Blocks
pin is high or the WPEN bit is “0”. When the device is
AT25128B/256B [Preliminary]
Protected
10). Upon completion, any data on the SI line will be
Protected
Protected
Protected
Protected
Protected
6000 – 7FFF
4000 – 7FFF
0000 – 7FFF
AT25256B
Table
None
8.
pin is low and the WPEN bit is “1”.
Unprotected
Protected
Protected
Protected
Writable
Writable
Writable
Blocks
) pin through the use of the write
Status Register
Protected
Protected
Protected
Protected
Writable
Writable
pin is
9