at49bv002an ATMEL Corporation, at49bv002an Datasheet - Page 4

• Manufacturer Part Number: at49bv002an
• Description: 2-megabit 256k X 8 Single 2.7-volt Battery-voltage Flash Memory
• Manufacturer: ATMEL Corporation

4.3
4.4
4.4.1
4.4.2
4.5
4
Reset
Erasure
Byte Programming
AT49BV002A(N)(T)
Chip Erase
Sector Erase
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET input halts the
present device operation and puts the outputs of the device in a high impedance state. If the
RESET pin makes a high to low transition during a program or erase operation, the operation
may not be successfully completed and the operation will have to be repeated after a high level
is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device
returns to the read or standby mode, depending upon the state of the control inputs. By applying
a 12V ± 0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if
the boot block lockout feature has been enabled (see
page
Before a byte can be reprogrammed, the main memory blocks or parameter blocks which con-
tains the byte must be erased. The erased state of the memory bits is a logical “1”. The entire
device can be erased at one time by using a 6-byte software code. The software chip erase
code consists of 6-byte load commands to specific address locations with a specific data pattern
(please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase opera-
tion so that no external clocks are required. The maximum time needed to erase the whole chip
is t
erased.
If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block
1, Parameter Block 2, Main Memory Block 1 - 4, but not the boot block. If the Boot Block Lockout
has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase
the device will return back to read mode. Any command during chip erase will be ignored.
As an alternative to a full chip erase, the device is organized into sectors that can be individually
erased. There are two 8K-byte parameter block sections and four main memory blocks. The 8K-
byte parameter block sections and the four main memory blocks can be independently erased
and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector
address is latched on the rising WE edge of the sixth cycle and the 30H data input command is
also latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the
sixth cycle. The erase operation is internally controlled; it will automatically time to completion.
Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte
basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is accomplished via the internal device command register
and is a 4 bus cycle operation (please refer to the
device will automatically generate the required internal program pulses.
EC
. If the boot block lockout feature has been enabled, the data in the boot sector will not be
5). The RESET feature is not available on the AT49BV002AN(T).
“Command Definition Table” on page
“Boot Block Programming Lockout” on
3353G–FLASH–8/05
7). The