at49f4096a ATMEL Corporation, at49f4096a Datasheet - Page 3

• Manufacturer Part Number: at49f4096a
• Description: 4-megabit 512k X 8/ 256k X 16 Flash Memory
• Manufacturer: ATMEL Corporation

AT49F4096A Block
Diagram
Device Operation
1604F–FLASH–4/04
READ: The AT49F4096A is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high-impedance state whenever
CE or OE is high. This dual line control gives designers flexibility in preventing bus
contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the
read or standby mode, depending upon the state of the control line inputs. In order to
perform other device functions, a series of command sequences are entered into the
device. The command sequences are shown in the Command Definitions table (I/O8 -
I/O15 are don’t care inputs for the command codes). The command sequences are writ-
ten by applying a low pulse on the WE or CE input with CE or WE low (respectively) and
OE high. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Standard microprocessor write
timings are used. The address locations used in the command sequences are not
affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When
RESET is at a logic high level, the device is in its standard operating mode. A low level
on the RESET input halts the present device operation and puts the outputs of the
device in a high-impedance state. When a high level is reasserted on the RESET pin,
the device returns to the read or standby mode, depending upon the state of the control
inputs. By applying a 12V ± 0.5V input signal to the RESET pin, the boot block array can
be reprogrammed even if the boot block program lockout feature has been enabled (see
“Boot Block Programming Lockout Override” section).
ERASURE: Before a byte or word can be reprogrammed, it must be erased. The erased
state of memory bits is a logic “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by using the Sector Erase
command.
CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip
erase software code. After the chip erase has been initiated, the device will internally
time the erase operation so that no external clocks are required. The maximum time to
erase the chip is t
ADDRESS
INPUTS
RESET
EC
GND
VCC
.
WE
OE
CE
Y DECODER
X DECODER
CONTROL
LOGIC
DATA INPUTS/OUTPUTS
PROGRAM DATA
INPUT/OUTPUT
MAIN MEMORY
(240K WORDS)
PARAMETER
PARAMETER
BOOT BLOCK
I/O0 - I/O15
4K WORDS
4K WORDS
BUFFERS
LATCHES
Y-GATING
8K WORDS
BLOCK 2
BLOCK 1
AT49F4096A
3FFFF
03FFF
02FFF
01FFF
00000
04000
03000
02000
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