is42s16100c1 Integrated Silicon Solution, Inc., is42s16100c1 Datasheet - Page 25

• Manufacturer Part Number: is42s16100c1
• Description: 512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S16100C1
Burst Read
The read cycle is started by executing the read command.
The address provided during read command execution is
used as the starting address. First, the data corresponding
to this address is output in synchronization with the clock
signal after the CAS latency period. Next, data corresponding
to an address generated automatically by the device is
output in synchronization with the clock signal.
The output buffers go to the LOW impedance state CAS
latency minus one cycle after the read command, and go
to the HIGH impedance state automatically after the last
data is output. However, the case where the burst length
Burst Write
The write cycle is started by executing the command. The
address provided during write command execution is used
as the starting address, and at the same time, data for this
address is input in synchronization with the clock signal.
Next, data is input in other in synchronization with the clock
signal. During this operation, data is written to address
generated automatically by the device. This cycle
terminates automatically after a number of clock cycles
determined by the stipulated burst length. However, the
case where the burst length is a full page is an exception.
In this case the write cycle must be terminated by executing
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. D
11/03/06
CAS
CAS
latency = 2,3, burst length = 4
latency = 3, burst length = 4
COMMAND
DQ8-DQ15
COMMAND
DQ0-DQ 7
UDQM
LDQM
CLK
CLK
DQ
READ (CA=A, BANK 0)
READ A0
D
WRITE
IN
0
DATA MASK (UPPER BYTE)
BURST LENGTH
D
IN
1
DATA MASK (LOWER BYTE)
t
QMD=2
D
D
OUT
OUT
D
IN
1-800-379-4774
A0
A0
2
is a full page is an exception. In this case the output
buffers must be set to the high impedance state by
executing a burst stop command.
Note that upper byte and lower byte output data can be
masked independently under control of the signals applied
to the U/LDQM pins. The delay period (t
regardless of the CAS latency setting, when this function
is used.
The selected bank must be set to the active state before
executing this command.
a burst stop command. The latency for DQ pin data input
is zero, regardless of the CAS latency setting. However, a
wait period (write recovery: t
required for the device to complete the write operation.
Note that the upper byte and lower byte input data can be
masked independently under control of the signals applied
to the U/LDQM pins. The delay period (t
regardless of the CAS latency setting, when this function
is used.
The selected bank must be set to the active state before
executing this command.
D
OUT
D
IN
HI-Z
A1
3
D
OUT
HI-Z
A2
D
OUT
A3
DPL
HI-Z
) after the last data input is
DMD
QMD
ISSI
) is fixed at zero,
) is fixed at two,
25
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