is42s16100-7tli Integrated Silicon Solution, Inc., is42s16100-7tli Datasheet - Page 29

• Manufacturer Part Number: is42s16100-7tli
• Description: 512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S16100
CAS latency = 3, burstlength = 4
Interval Between Write and Read Commands
A new read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
corresponding to the new read command is output after
the CAS latency has elapsed from the point the new read
command was executed. The I/On pins must be placed in
the HIGH impedance state at least one cycle before data
is output during this operation.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
01/28/08
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
CLK
DQ
DQ
WRITE (CA=A, BANK 0)
WRITE (CA=A, BANK 0)
D
D
WRITE A0 READ B0
WRITE A0 READ B0
IN
IN
A0
A0
t
t
CCD
CCD
READ (CA=B, BANK 0)
READ (CA=B, BANK 0)
HI-Z
D
OUT
HI-Z
B0
The interval (t
one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
D
OUT
OUT
B1
B0
D
D
OUT
OUT
ccd
B2
B1
) between command must be at least
D
D
OUT
OUT
B2
B3
D
OUT
B3
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