is42s16800al-7tli Integrated Silicon Solution, Inc., is42s16800al-7tli Datasheet - Page 30

• Manufacturer Part Number: is42s16800al-7tli
• Description: 128-mbit Low-power Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

CAS LATENCY
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n + m. The DQs will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant
access times are met, the data will be valid by clock edge
n + m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ
command is registered at T0 and the latency is programmed
to two clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in CAS Latency diagrams. The
Allowable Operating Frequency table indicates the operat-
ing frequencies at which each CAS latency setting can be
used.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
30
COMMAND
COMMAND
CLK
CLK
DQ
DQ
READ
READ
T0
T0
Integrated Silicon Solution, Inc. — www.issi.com —
CAS Latency - 2
NOP
NOP
CAS Latency - 3
T1
T1
t
LZ
t
AC
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
CAS Latency
S p e e d
Allowable Operating Frequency (MHz)
NOP
NOP
10
T2
T2
7
D
OUT
t
t
OH
LZ
t
AC
CAS Latency = 2
NOP
T3
T3
D
DON'T CARE
UNDEFINED
OUT
t
OH
PRELIMINARY
100
100
T4
INFORMATION
CAS Latency = 3
ISSI
1-800-379-4774
133
100
Rev. 00A
09/18/03
®