is42s16800al-7tli Integrated Silicon Solution, Inc., is42s16800al-7tli Datasheet - Page 8
![no-image](/images/no-image-200.jpg)
is42s16800al-7tli
Manufacturer Part Number
is42s16800al-7tli
Description
128-mbit Low-power Synchronous Dram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
1.IS42S16800AL-7TLI.pdf
(67 pages)
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
PIN FUNCTIONS
DQM0-DQM3
8
BA0, BA1
Symbol
A0-A11
DQML,
DQMH
DQM
RAS
CAS
CKE
V
V
CLK
V
V
WE
CS
DDQ
SSQ
DD
SS
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Type
Integrated Silicon Solution, Inc. — www.issi.com —
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A9 (x8); A0-A8
(x16); A0-A7 (x32) with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command
to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0,
BA1 (A10 LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when CS is HIGH.
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode,DQML and DQMH control the input buffer.
WhenDQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. WhenDQML or DQMH is HIGH, input data is masked and
cannot be written to the device.
For IS42S32400AL, IS42S32400AL only.
For IS42S81600AL, IS42S81600AL only.
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
V
V
V
V
DDQ
DD
SSQ
SS
is the device internal ground.
is the device internal power supply.
is the output buffer ground.
is the output buffer power supply.
PRELIMINARY
INFORMATION
ISSI
1-800-379-4774
Rev. 00A
09/18/03
®