is42s16400f-5tli Integrated Silicon Solution, Inc., is42s16400f-5tli Datasheet - Page 5

• Manufacturer Part Number: is42s16400f-5tli
• Description: 1 Meg Bits X 16 Bits X 4 Banks 64-mbit Synchronous Dynamic Ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S16400F, IC42S16400F
IS45S16400F
FUNCTION (In Detail)
A0-A11 are address inputs sampled during the ACTIVE
(row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto PRECHARGE). A10 is sampled during
a PRECHARGE command to determine if all banks are to
be PRECHARGED (A10 HIGH) or bank selected by BA0,
BA1 (LOW). The address inputs also provide the op-code
during a LOAD MODE REGISTER command.
Bank Select Address (BA0 and BA1) defines which bank
the ACTIVE, READ, WRITE or PRECHARGE command
is being applied.
CAS, in conjunction with the RAS and WE, forms the device
command. See the “Command Truth Table” for details on
device commands.
The CKE input determines whether the CLK input is en-
abled. The next rising edge of the CLK signal will be valid
when is CKE HIGH and invalid when LOW. When CKE is
LOW, the device will be in either power-down mode, CLOCK
SUSPEND mode, or SELF-REFRESH mode. CKE is an
asynchronous input.
CLK is the master clock input for this device. Except for
CKE, all inputs to this device are acquired in synchroniza-
tion with the rising edge of this pin.
The CS input determines whether command input is en-
abled within the device. Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when CS is HIGH. DQ0 to
DQ15 are DQ pins. DQ through these pins can be controlled
in byte units using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of
the DQ buffers. In read mode, LDQM and UDQM control
the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH,
disabled. The outputs go to the HIGH Impedance State
when LDQM/UDQM is HIGH. This function corresponds
to OE in conventional DRAMs. In write mode, LDQM and
UDQM control the input buffer. When LDQM or UDQM is
LOW, the corresponding buffer byte is enabled, and data
can be written to the device. When LDQM or UDQM is
HIGH, input data is masked and cannot be written to the
device.
RAS, in conjunction with CAS and WE , forms the device
command. See the “Command Truth Table” item for details
on device commands.
WE , in conjunction with RAS and CAS , forms the device
command. See the “Command Truth Table” item for details
on device commands.
V
V
GND
GND is the device internal ground.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/08
DDQ
DD
is the device internal power supply.
Q
is the output buffer power supply.
is the output buffer ground.
READ
The READ command selects the bank from BA0, BA1 inputs
and starts a burst read access to an active row. Inputs
A0-A7 provides the starting column location. When A10 is
HIGH, this command functions as an AUTO PRECHARGE
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank,
and the starting column location is provided by inputs
A0-A7. Whether or not AUTO-PRECHARGE is used is
determined by A10.
The row being accessed will be precharged at the end of
AUTO PRECHARGE is not selected, the row will remain
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determined
whether one or all banks are precharged. After execut-
ing this command, the next command for the selected
banks(s) is executed after passage of the period t
is the period required for bank precharging. Once a bank
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the pre-
charge is initiated at the earliest valid stage within a burst.
This function allows for individual-bank precharge without
command. When the auto precharge is selected, the row
being accessed will be precharged at the end of the READ
burst. The row will remain open for subsequent accesses
when AUTO PRECHARGE is not selected. DQ’s read
data is subject to the logic level on the DQM inputs two
clocks earlier. When a given DQM signal was registered
HIGH, the corresponding DQ’s will be High-Z two clocks
later. DQ’s will provide valid data when the DQM signal
was registered LOW.
the WRITE burst, if AUTO PRECHARGE is selected. If
open for subsequent accesses.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
requiring an explicit command. A10 to enables the AUTO
PRECHARGE function in conjunction with a specific READ
or WRITE command. For each individual READ or WRITE
command, auto precharge is either enabled or disabled.
RP
, which
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