is42s16400b1 Integrated Silicon Solution, Inc., is42s16400b1 Datasheet - Page 6

• Manufacturer Part Number: is42s16400b1
• Description: 1 Meg Bits X 16 Bits X 4 Banks 64-mbit Synchronous Dynamic Ram - Integrated Silicon Solution, Inc
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S16400B1
6
TRUTH TABLE – COMMANDS AND DQM OPERATION
NOTES:
1. CKE is HIGH for all commands except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
FUNCTION
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank/column, start READ burst)
WRITE (Select bank/column, start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
auto precharge; BA0, BA1 determine which bank is being read from or written to.
(2)
(8)
(8)
(6,7)
(3)
(4)
(4)
(5)
Integrated Silicon Solution, Inc. — www.issi.com —
CS
CS
CS
CS
CS
—
—
H
L
L
L
L
L
L
L
L
RAS
RAS
RAS
RAS
RAS
—
—
H
H
H
H
X
L
L
L
L
CAS
CAS
CAS
CAS
CAS
—
—
X
H
H
H
H
L
L
L
L
(1)
WE
WE
WE
WE
WE
—
—
X
H
H
H
H
L
L
L
L
DQM
L/H
L/H
H
X
X
X
X
X
X
X
L
(8)
(8)
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
—
—
X
X
X
X
ISSI
1-800-379-4774
High-Z
Active
Active
Valid
DQs
12/09/03
X
X
X
X
X
X
X
Rev. A
®