m95128 STMicroelectronics, m95128 Datasheet - Page 43

• Manufacturer Part Number: m95128
• Description: 128 Kbit Serial Spi Bus Eeprom With High Speed Clock
• Manufacturer: STMicroelectronics

M95128, M95128-W, M95128-R
Table 25.
27-Jun-2006
15-Jan-2008
13-Apr-2006
04-Oct-2007
Date
Document revision history (continued)
Revision
6
7
8
9
New M95128 datasheet extracted from the M95128/256 datasheet. Order
of sections modified.
ECC (error correction code) and Write cycling
Section 3.8: Supply voltage (VCC)
Section 4: Operating
Power up state removed below
Figure 13: SPI modes supported
I
Table 14
I
t
Figure 16: Hold timing
Process
scheme.
“AC Characteristics (M95128, Device Grade
frequency) removed.
Note 1 removed from
T
PDIP8 (BN) and SO8 wide (MW) packages removed. M95128-W and
M95128-R are no longer under development.
Test conditions changed for V
characteristics (M95128-W, device grade
Figure 12: Bus master and memory devices on the SPI bus
SO8N package specifications updated (see
V Process specified and A Process replaced by P in
information
Section 3.8: Supply voltage
protocol
Write to Memory Array (WRITE)
code) and Write cycling
Note removed below
SPI
Test conditions modified for I
(M95128-R). AC characteristics values added for f
Table 16: AC characteristics (M95128, device grade
t
Section 10: Package
– UFDFPN8 package added
– Package mechanical inch values calculated from mm and rounded to 4
Table 24: Available M95128x products (package, voltage range,
temperature grade)
Blank removed below Plating technology, first note removed, process A
added and process V removed in
Section 3.7: VSS ground
Section 3.8.4: Power-down
and Write cycling
V
Table 24: Available M95128x products (package, voltage range,
temperature grade)
CC1
CC
CHHL
W
A
IL
decimal digits
modified in
added to
and V
specified over the whole V
bus, replaced by paragraph.
specified over the whole V
and t
control,
letter and
and
IH
CHHH
scheme.
modified in
Table 6: Absolute maximum
Table
Table 19: AC characteristics
Section 5.4: Write Status Register
replaced by t
modified.
Note 1
15.
added.
updated.
features.
Figure 12: Bus master and memory devices on the
mechanical:
Table 19: AC characteristics
modified.
Table 15: DC characteristics
updated.
added.
added to
and
(VCC),
CC1
OL
CLHL
CC
CC
Section 6: Delivery
Section 5.6.1: ECC (error correction code)
Changes
and V
and
and I
Section 3.8.3: Device
modified and
range in
Table 23: Ordering information
range and I
added and information removed below
and t
Section 4.3: Data Protection and
Table 23: Ordering information
Section 5.6.1: ECC (error correction
CC0
OH
CLHH
ratings.
3).
in
in
Table
(M95128-R).
Table 20
Section Table 14.: DC
Table 15: DC characteristics
6)” Table (for 10MHz
, respectively.
CC0
paragraph added.
Note 2
13.
C
added to
(M95128-R).
state.
frequency = 10 MHz in
(WRSR),
3).
(M95128-R).
Table 23: Ordering
and
added.
reset,
Revision history
Figure
Table
modified.
Section 5.6:
18).
scheme.
13,
43/44