m28w640fcb STMicroelectronics, m28w640fcb Datasheet - Page 7

• Manufacturer Part Number: m28w640fcb
• Description: 64 Mbit 4mb X16, Boot Block 3v Supply Flash Memory
• Manufacturer: STMicroelectronics

M28W640FCT, M28W640FCB
1
Summary description
The M28W640FCT and M28W640FCB are 64 Mbit (4 Mbit x 16) non-volatile Flash
memories that can be erased electrically at block level and programmed in-system on a
Word-by-Word basis using a 2.7V to 3.6V V
V
speed up customer programming.
The devices feature an asymmetrical blocked architecture. They have an array of 135
blocks: 8 Parameter Blocks of 4 KWord and 127 Main Blocks of 32 KWord. The
M28W640FCT has the Parameter Blocks at the top of the memory address space while the
M28W640FCB locates the Parameter Blocks starting from the bottom. The memory maps
are shown in
The M28W640FCT and M28W640FCB feature an instant, individual block locking scheme
that allows any block to be locked or unlocked with no latency, enabling instant code and
data protection. All blocks have three levels of protection. They can be locked and locked-
down individually preventing any accidental programming or erasure. There is an additional
hardware protection against program and erase. When V
against program or erase. All blocks are locked at Power Up.
Each block can be erased separately. Erase can be suspended in order to perform either
read or program in any other block and then resumed. Program can be suspended to read
data in any other block and then resumed. Each block can be programmed and erased over
100,000 cycles.
The device includes a 192 bit Protection Register to increase the protection of a system
design. The Protection Register is divided into a 64 bit segment and a 128 bit segment. The
64 bit segment contains a unique device number written by ST, while the second one is one-
time-programmable by the user. The user programmable segment can be permanently
protected.
Program and Erase commands are written to the Command Interface of the memory. An on-
chip Program/Erase Controller takes care of the timings necessary for program and erase
operations. The end of a program or erase operation can be detected and any error
conditions identified. The command set required to control the memory is consistent with
JEDEC standards.
The memory is offered in TSOP48 (12 × 20mm) and TFBGA48 (6.39 × 10.5mm, 0.75mm
pitch) packages and is supplied with all the bits erased (set to ’1’).
In order to meet environmental requirements, ST offers the M28W640FCT and
M28W640FCB in ECOPACK® packages. These packages have a Lead-free second level
interconnect. The category of second Level Interconnect is marked on the package and on
the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
DDQ
supply for the Input/Output pins. An optional 12V V
Figure
Figure 4: Block
5, shows the Protection Register Memory Map.
addresses.
DD
supply for the circuitry and a 1.65V to 3.6V
PP
PP
power supply is provided to
V
PPLK
all blocks are protected
Summary description
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