74ABT574CMSAX Fairchild Semiconductor, 74ABT574CMSAX Datasheet

IC FLIP FLOP OCT D 3ST 20SSOP

74ABT574CMSAX

Manufacturer Part Number
74ABT574CMSAX
Description
IC FLIP FLOP OCT D 3ST 20SSOP
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Type
D-Type Busr
Datasheet

Specifications of 74ABT574CMSAX

Function
Standard
Output Type
Tri-State Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
200MHz
Delay Time - Propagation
3.2ns
Trigger Type
Positive Edge
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2005 Fairchild Semiconductor Corporation
74ABT574CSC
74ABT574CSJ
74ABT574CMSA
74ABT574CMTC
74ABT574
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT574 is an octal flip-flop with a buffered common
Clock (CP) and a buffered common Output Enable (OE).
The information presented to the D inputs is stored in the
flip-flops on the LOW-to-HIGH Clock (CP) transition.
The device is functionally identical to the ABT374 but has
broadside pinouts.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Order Number
Package Number
MSA20
MTC20
M20D
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS011511
Features
Pin Descriptions
D
CP
OE
O
Pin Names
0
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
Useful as input or output port for microprocessors
Functionally identical to ABT374
3-STATE outputs for bus-oriented applications
Output sink capability of 64 mA, source capability
of 32 mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and
250 pF loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Non-destructive hot insertion capability
0
–D
–O
7
7
Package Description
Data Inputs
Clock Pulse Input (Active Rising Edge)
3-STATE Output Enable Input (Active LOW)
3-STATE Outputs
November 1992
Revised March 2005
Description
www.fairchildsemi.com

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74ABT574CMSAX Summary of contents

Page 1

... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram © 2005 Fairchild Semiconductor Corporation Features Inputs and outputs on opposite sides of package allowing easy interface with microprocessors ...

Page 2

Functional Description The ABT574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2)  Input Current (Note Voltage Applied to Any Output in the Disabled ...

Page 4

DC Electrical Characteristics (SOIC Package) Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V ...

Page 5

Extended AC Electrical Characteristics (SOIC Package) Symbol Parameter t Propagation Delay PLH PHL n t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ Note 8: This specification is guaranteed but not ...

Page 6

AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude 3.0V FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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