w9425g8dh Winbond Electronics Corp America, w9425g8dh Datasheet - Page 11

• Manufacturer Part Number: w9425g8dh
• Description: 8m ? 4 Banks ? 8 Bits Ddr Sdram
• Manufacturer: Winbond Electronics Corp America

7.2.11 Burst Read Stop Command
7.2.12 Device Deselect Command
7.2.13 Auto Refresh Command
7.2.14 Self Refresh Entry Command
7.2.15 Self Refresh Exit Command
( RAS = "H", CAS = "H", WE = "L")
The Burst stop command is used to stop the burst operation. This command is only valid during a
Burst Read operation.
( CS = "H")
The Device Deselect command disables the command decoder so that the RAS , CAS ,
( RAS = "L", CAS = "L", WE = "H", CKE = "H", BS0, BS1, A0 to A12 = Don’t Care)
( RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = Don’t Care)
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of
the system is powered down. When in the self refresh mode, the DDR SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF
REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is
enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command
can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is
an SSTL_2 input,
(CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H")
The use of SELF REFREH mode introduces the possibility that an internally timed event can be
missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an
extra auto refresh command is recommended.
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS–
BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it
must be issued each time a refresh is required. The refresh addressing is generated by the
internal refresh controller. This makes the address bits ”Don’t Care” during an AUTO REFRESH
command. The DDR SDRAM requires AUTO REFRESH cycles at an average periodic interval of
tREFI (maximum). To allow for improved efficiency in scheduling and switching between tasks,
some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, and the maximum absolute interval
between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * t
WE and Address inputs are ignored. This command is similar to the No-Operation command.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be
stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP
commands issued for t
progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for
200 clock cycles before applying any other command.
V
REF
must be maintained during SELF REFRESH.
XSNR
because time is required for the completion of any internal refresh in
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Publication Release Date: Nov. 20
Revision A4
REFI
,
2007
.