w9425g8dh Winbond Electronics Corp America, w9425g8dh Datasheet - Page 4

• Manufacturer Part Number: w9425g8dh
• Description: 8m ? 4 Banks ? 8 Bits Ddr Sdram
• Manufacturer: Winbond Electronics Corp America

1. GENERAL DESCRIPTION
W9425G8DH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 8,388,608 words × 4 banks × 8 bits. Using pipelined architecture and 0.11 µm
process technology, W9425G8DH delivers a data bandwidth of up to 400M words per second (-5). To
fully comply with the personal computer industrial standard, W9425G8DH is sorted into three speed
grades: -5, -6 and -75. The -5 is compliant to the DDR400/CL3 specification, the -6 is compliant to the
DDR333/CL2.5 specification and the -75 is compliant to the DDR266/CL2 specification.
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. Write and
Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9425G8DH is ideal for main memory in
high performance applications.
2. FEATURES
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2.5V ±0.2V Power Supply for DDR266
2.5V ±0.2V Power Supply for DDR333
2.6V ±0.1V Power Supply for DDR400
Up to 200 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and CLK )
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5 and 3
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
7.8µS refresh interval (8K / 64mS refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2
Packaged in TSOP II 66-pin, 400 mil, 0.65 mm pin pitch, using Pb free with RoHS compliant
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Publication Release Date: Nov. 20
Revision A4
,
2007