nanda9w3n7 Numonyx, nanda9w3n7 Datasheet
nanda9w3n7
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nanda9w3n7 Summary of contents
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... NANDA9R4Nx NANDBAR3Nx NANDB9R3N0 Rev 10 NANDxxRxNx FBGA TFBGA107 10.5 × 13 × 1.2 mm TFBGA137 10 1.2 mm TFBGA149 10 × 13.5 × 1.2 mm VFBGA160 TFBGA TFBGA152 14×14 × 1.1 mm TFBGA152 14 × 14 × 1.2 mm TFBGA128 1.1 mm Device summary NANDxxRxNx NANDA8R3N0 NANDA9R3Nx NANDA9WxN1 NANDB0R3N0 NANDBAR4Nx NANDB1R3N0 NANDB9R4Nx NANDC9R4N0 www.numonyx.com 1/46 1 ...
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... Flash memory inputs/outputs (I/O0-I/O7 2.2 Flash memory inputs/outputs (I/O8-I/O15 2.3 Flash memory Address Latch Enable (AL 2.4 Flash memory Command Latch Enable (CL 2.5 Flash memory Chip Enable (E 2.6 Flash memory Read Enable ( 2.7 Flash memory Write Enable (W 2.8 Flash memory Write Protect (WP 2.9 Flash memory Ready/Busy (RB 2.10 Flash memory V 2.11 LPSDRAM Address inputs (A0-Ax) ...
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NANDxxRxNx 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NANDxxRxNx List of figures Figure 1. Block diagram for TFBGA107, TFBGA137, and TFBGA149 packages . . . . . . . . . . . . . . . 10 Figure 2. Block diagram for TFBGA128, TFBGA152 (NANDA8R3N0, NANDA9R3N0, NANDBAR3N1) ...
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... Description 1 Description The NANDxxRxNx devices combine multiple memory devices in a multichip package or a package-on-package solution that includes: 1.8/2.6 V supply 1-or 2-Gbit (x8/x16), or 1.8 V supply 2 x 2-Gbit (×16), NAND flash memories (NAND01GWxB2B, NAND01GRxB2B, NAND01GRxB2C, NAND02GRxB2C, NAND02GRxB2D) 128-Mbit (x16) SDR (single data rate) LPSDRAM (M65KA128AJ) + 256-Mbit (x16) ...
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... TFBGA107 (10.5 × 13 × 1.2 mm) TFBGA137 (10 1.2 mm) TFBGA152 (14 × 14 × 1.1 mm) and TFBGA152 (14 × 14 × 1.2 mm) TFBGA149 (10 × 13.5 × 1.2 mm) TFBGA128 ( 1.1 mm) VFBGA160 ( mm) The memories are supplied with all the NAND flash memory bits erased (set to ‘1’). Table 2: Product list: Description 7/46 ...
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Description Table 2. Product list Reference Part number NANDA0R3N0 NANDA0R3N0 NANDA8R3N0 NANDA8R3N0 NANDA9R3N0 NANDA9R3N1 NANDA9R3Nx NANDA9R3N2 NANDA9R3N3 NANDA9R3N6 NANDA9R4N0 NANDA9R4N1 NANDA9R4N2 NANDA9R4Nx NANDA9R4N3 NANDA9R4N4 NANDA9R4N6 NANDA9W3N1 NANDA9WxN1 NANDA9W4N1 NANDB0R3N0 NANDB0R3N0 NANDBAR3N1 NANDBAR3Nx NANDBAR3N6 8/46 LPSDRAM NAND product product SDR 128 ...
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NANDxxRxNx Table 2. Product list (continued) NANDBAR4N0 NANDBAR4N1 NANDBAR4Nx NANDBAR4N2 NANDBAR4N5 NANDBAR4N7 NANDB1R3N0 NANDB1R3N0 NANDB9R3N0 NANDB9R3N0 NANDB9R4N0 NANDB9R4Nx NANDB9R4N5 NANDC9R4N0 NANDC9R4N0 2x2 Gbits (x16 SDR = single data rate. 2. DDR = double data rate. SDR ...
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Description Figure 1. Block diagram for TFBGA107, TFBGA137, and TFBGA149 packages 1. Only available in MCP with DDR x32. 2. Only available in MCP with DDR. 3. Only available in MCP with SDR/DDR x32. 4. Only available in MCP with ...
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NANDxxRxNx Figure 2. Block diagram for TFBGA128, TFBGA152 (NANDA8R3N0, NANDA9R3N0, NANDBAR3N1) and VFBGA160 packages 1. Only available in PoP with DDR. 2. Only available in PoP with DDRx16. 3. Only available in PoP with SDR/DDR x32 ...
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Description Figure 3. Block diagram for TFBGA152 package (NANDBxR3N0, NANDA0R3N0) 1. D1-X signals are related to the 128-Mbit SDR, while D2-X signals are related to the 256- or 512-Mbit SDR. 12/ DDQD DDD 12 D1-A0-A11 13 D2-A0-A12 2 ...
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... Only available with DDR x32. 2. Only available with DDR. 3. Only available with SDR/DDR x32. 4. Only available with DDR x16. Function NAND flash memory Data input/outputs (x8/x16) Data inputs/outputs (x16) Address Latch Enable Command Latch Enable Chip Enable Read Enable Ready/Busy (open-drain output) ...
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Description Figure 4. TFBGA107 connections (top view through package SSD V DDQD D V SSQD E V DDQD F V SSD G V DDD H V SSQD UDQS ...
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NANDxxRxNx Figure 5. TFBGA128 connections (top view through package DQ1 DDF NC V DDQD B DQ0 V DDD V SS DQ2 DQ3 DQ4 D DQ5 V DDQD ...
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Description Figure 6. TFBGA137 connections (top view through package SSD DDD A12 A11 F NC RAS G V DDD CAS H V SSD E ...
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NANDxxRxNx Figure 7. TFBGA149 connections (top view through package SSF ...
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Description Figure 8. TFBGA152 connections - NANDA8R3N0, NANDA9R3N0 (top view through package DQ7 DQ6 DQ3 DDQ DQ5 DQ4 V SS DQ8 C BA0 DQM0 D ...
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NANDxxRxNx Figure 9. TFBGA152 connections - NANDBxR3N0, NANDA0R3N0 (top view through package D1- D1- D1- D1 DQ6 DQ1 DQ7 DQ3 D1- D1- D1 DDQD V DDD V DDD ...
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Description Figure 10. TFBGA152 connections - NANDBAR3N1 (top view through package DDQD DQM1 DQ13 DQ15 DQ6 DQ7 V DDQD DQ3 DQ5 D DQ0 DQ1 ...
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NANDxxRxNx Figure 11. VFBGA160 connections - NANDBAR4N2 (top view through package DDD DQ1 ...
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... Write Enable. 2.4 Flash memory Command Latch Enable (CL) The Command Latch Enable activates the latching of the command inputs in the command Interface of the NAND flash memory. When CL is high, the inputs are latched on the rising edge of Write Enable. 2.5 Flash memory Chip Enable (E The NAND flash memory Chip Enable input activates the memory control logic, input buffers, decoders, and sense amplifiers ...
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... A Low then indicates that one or more of the memories is busy. 2.10 Flash memory V V provides the power supply to the internal core of the NAND flash memory device DDF the main power supply for all operations (read, program and erase). 2.11 LPSDRAM Address inputs (A0-Ax) The A0-Ax address inputs are used by the LPSDRAM to select the row or column to be made active. If A10 is High (set to ‘ ...
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Signal descriptions When selecting the addresses the LPSDRAM must be enabled, the Row Address Strobe, RAS, must be Low, V 2.13 LPSDRAM Data inputs/outputs (DQ0-DQ31) On the LPSDRAM, DQ0-DQ31 output the data stored at the selected address during a read ...
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NANDxxRxNx 2.19 LPSDRAM Clock Input (K) The Clock signal only available on the DDR LPSDRAM used in conjunction with the Clock signal, K. All LPSDRAM input signals except DQM0/DQM1/DQM2/DQM3, UDQS/LDQS and DQ0- DQ31 are referred to ...
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... LPSDRAM input/output circuitry driven by V SSQD V must be connected to V SSQD 2.26.2 NANDxxRxNx delivered in TFBGA128/152 and VFBGA160 packages The NAND flash memory and LPSDRAM components share the same ground V described below. V ground SS V ground is the reference for the power supply for the NAND flash and LPSDRAM SS components ...
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... NANDxxRxNx 3 Functional description The NAND flash memory and LPSDRAM components have separate power supplies and, according to in which package they are delivered, they either share the same grounds or have separate grounds. They also have separate control signals, addresses, and data input/outputs, which allows simultaneous access to both devices at any time. ...
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... Figure 12. Functional block diagram for TFBGA107, TFBGA137, TFBGA149 packages 1. Only available in MCP with DDR x16. 2. Only available in MCP with DDR x32. 3. Only available in MCP with SDR/DDR x32. 4. Only available in MCP with DDR LPSDRAM. 28/46 V DDF NAND flash E F memory SSF V V DDD DDQD 2 BA0-BA1 13 A0-A12 16 ...
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... Figure 13. Functional block diagram for TFBGA128 (NANDA9R3N0, NANDB9R3N0), TFBGA152 (NANDA8R3N0, NANDA9R3N0, NANDBAR3N1) and VFBGA160 packages 1. Only available in PoP with DDR x16. 2. Only available in PoP with DDR/SDR x32. 3. Only available in PoP with DDR LPSDRAM. V DDF NAND flash memory DDQD DDD 2 BA0-BA1 12 A0-A11 ...
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... Functional description Figure 14. Functional block diagram for TFBGA152 (NANDBxR3N0, NANDA0R3N0) package 2 BA0-BA1 12 A0-A11 CAS RAS DQM0 DQM1 30/46 V DDF NAND flash memory DDQD DDD 16 DQ0-DQ15 128-Mbit SDR V SS NANDxxRxNx 8 I/O0-I/ 256- or 512-Mbit SDR DQM0 ...
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... NANDxxRxNx Figure 15. Functional block diagram for TFBGA128 (NANDBAR3N6) package 2 BA0-BA1 13 A0-A12 CAS RAS DQM0 DQM1 V DDF NAND flash memory DDQD DDD 16 DQ0-DQ15 512-Mbit SDR V SS Functional description 8 I/O0-I/ 512-Mbit SDR DQM0 DQM1 DQ0-DQ15 ...
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... For detailed information on the LPSDRAM parameters, refer to the M65KA512AB, M65KA512AC, M65KG512AB, M65KA256AG, M65KC512AB, M65KC512AC, M65KD512AC, M65KAxxxAJ, M65KA512AH, M65KG512AH, M65KGxxxAJ, M65KAxxxAM, M65KCxxxAJ, M65KDxxxAJ, and M65KGxxxAM datasheets available from your local Numonyx sales office. 32/46 inTable 4: Absolute maximum ratings (1) Parameter Ambient operating temperature ...
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... NANDxxRxNx 5 Package mechanical To meet environmental requirements, Numonyx offers these devices in ECOPACK packages. ECOPACK is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 16. TFBGA107 10.5 × × 14 active ball array, 0.80 mm pitch, package outline ...
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Package mechanical Table 5. TFBGA107 10.5 × × 14 active ball array, 0.80 mm pitch, mechanical data Symbol Typ 0.80 b 0.45 D 10.50 D1 7.20 ddd E 13.00 E1 10.40 e 0.80 ...
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NANDxxRxNx Figure 17. TFBGA128 - 2-row perimeter matrix 2R18 × 18, 12 × 12 mm, 0.65 mm pitch, package outline E 1. Drawing is not to scale Package mechanical e b ddd ...
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Package mechanical Table 6. TFBGA128 - 2-row perimeter matrix 2R18 × 18, 12 × 12 mm, 0.65 mm pitch, mechanical data Symbol Typ 0.63 b 0.42 D 12.00 D1 11.05 ddd E 12.00 E1 11.05 e 0.65 ...
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NANDxxRxNx Figure 18. TFBGA137 10 active ball array, 0.80 mm pitch, package outline E E1 BALL "B1" 1. Drawing is not to scale. Table 7. TFBGA137 10 ...
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Package mechanical Figure 19. TFBGA149 10 × 13 × 16 active ball array, 0.80 mm pitch, package outline BALL "A1" Drawing not to scale. Table 8. TFBGA149 10 × 13.5 mm ...
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NANDxxRxNx Figure 20. TFBGA152, 2-row perimeter matrix 2R21 x 21 1.1 mm, 0.65 mm pitch, package outline Drawing is not to scale. Table 9. TFBGA152, 2-row perimeter matrix 2R21 x 21, 14 ...
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Package mechanical Figure 21. TFBGA152, 2-row perimeter matrix 2R21 x 21, 14 × 1.2 mm, 0.65 mm pitch, package outline Drawing is not to scale. Table 10. TFBGA152, 2-row perimeter matrix 2R21 x 21, 14 ...
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NANDxxRxNx Figure 22. VFBGA160 15 × mm, 0.65 mm pitch, package outline Drawing not to scale. Table 11. VFBGA160 15 × mm, 0.65 mm pitch, mechanical data Symbol ...
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... Ordering information 6 Ordering information Table 12. Ordering information scheme Example: Device type NAND flash memory NAND flash density Gbit Gbits Gbits DRAM density 9 = 512 Mbits 8 = 256 Mbits Gbit 0 = 128 Mbits + 512 Mbits 1 = 128 Mbits + 256 Mbits NAND flash operating voltage ...
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... NANDxxRxNx Note: Devices are shipped from the factory with the flash memory content bits, in valid blocks, erased to ’1’. For further information on any aspect of this device, please contact your nearest Numonyx sales office. Ordering information 43/46 ...
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... V throughout the document. Modified connections (top view through package) Figure 12 to add 4-Gbit option and notes. Also added notes to 6 Applied Numonyx branding. Added root part numbers NANDB0R3N0 and NANDB1R3N0 throughout the document. 7 Minor text changes. Added root part numbers NANDBAR4N0, NANDBAR4N1 and 8 NANDBAR4N2 throughout the document ...
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NANDxxRxNx Table 13. Document revision history (continued) Date Version 06-Aug-2008 14-Aug-2008 Modified datasheet’s title. Added root part numbers NANDBAR4N5, NANDA0R3N0, 9 NANDA9R3N6, and NANDBAR4N7 throughout the document. Removed TFBGA160 1.2 mm and added VFBGA160 15 x ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...