nanda9w3n7 Numonyx, nanda9w3n7 Datasheet - Page 23

• Manufacturer Part Number: nanda9w3n7
• Description: Large Page Nand Flash Memory And Low Power Sdram, 1.8/2.6 V Mcp And Pop
• Manufacturer: Numonyx

NANDxxRxNx
2.6
2.7
2.8
2.9
2.10
2.11
2.12
Flash memory Read Enable (R)
The NAND flash memory Read Enable pin, R, controls the sequential data output during
read operations. The falling edge of R also increments the internal column address counter
by one.
Flash memory Write Enable (W
The NAND flash memory Write Enable input, W
input address, and data latches. Both addresses and data are latched on the rising edge of
Write Enable.
Flash memory Write Protect (WP)
The Write Protect pin is a NAND flash memory input that gives a hardware protection
against unwanted program or erase operations. When Write Protect is Low, V
flash memory device does not accept any program or erase operations.
It is recommended to keep the Write Protect pin Low, V
Flash memory Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain NAND flash memory output that can be used
to identify if the P/E/R controller is currently active.
When Ready/Busy is Low, V
operation completes Ready/Busy goes High, V
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low then indicates that one or more of the
memories is busy.
Flash memory V
V
the main power supply for all operations (read, program and erase).
LPSDRAM Address inputs (A0-Ax)
The A0-Ax address inputs are used by the LPSDRAM to select the row or column to be
made active. If A10 is High (set to ‘1’) during read or write, the read or write cycle operation
includes an auto precharge cycle. If A10 is Low (set to ‘0’) during read or write, the read or
write cycle does not include an auto precharge cycle.
LPSDRAM Bank Select Address inputs (BA0-BA1)
The BA0 and BA1 banks select address inputs are used by the LPSDRAM to select the
bank to be made active.
DDF
provides the power supply to the internal core of the NAND flash memory device. It is
DDF
OL
supply voltage
, a read, program or erase operation is in progress. When the
F
OH
F
)
, controls writing to the command interface,
.
IL
, during power-up and power-down.
Signal descriptions
IL
, the NAND
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