m48z12 STMicroelectronics, m48z12 Datasheet - Page 7

• Manufacturer Part Number: m48z12
• Description: 5v, 16kbit 2kb X 8 Zeropower Sram
• Manufacturer: STMicroelectronics

2
Note:
2.1
Operation modes
The M48Z02/12 also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single 5V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
approximately 3V, the control circuitry connects the battery which maintains data operation
until valid power returns.
Table 2.
1. See
X = V
Read mode
The M48Z02/12 is in the READ Mode whenever W (WRITE Enable) is high and E (Chip
Enable) is low. The device architecture allows ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the unique address specified by the 11
Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data
will be available at the Data I/O pins within Address Access time (t
address input signal is stable, providing that the E and G access times are also satisfied. If
the E and G access times are not met, valid data will be available after the latter of the Chip
Enable Access time (t
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are
activated before t
the Address Inputs are changed while E and G remain active, output data will remain valid
for Output Data Hold time (t
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
IH
Table 10 on page 16
or V
IL
Operating modes
V
; V
SO
4.75 to 5.5V
SO
4.5 to 5.5V
to V
AVQV
≤ V
= Battery back-up switchover voltage.
V
PFD
or
SO
CC
ELQV
, the data lines will be driven to an indeterminate state until t
(1)
for details.
(min)
) or Output Enable Access time (t
AXQX
(1)
) but will go indeterminate until the next Address Access.
V
V
V
V
E
X
X
IH
IL
IL
IL
V
V
G
X
X
X
X
IH
IL
V
V
V
W
X
X
X
IH
IH
IL
GLQV
CC
High Z
High Z
High Z
High Z
D
DQ0-
DQ7
. As V
D
OUT
IN
).
AVQV
CC
Battery back-up mode
) after the last
CC
falls below
CMOS standby
is out of
Standby
Power
Active
Active
Active
AVQV
. If
7/20