m58lw032a STMicroelectronics, m58lw032a Datasheet
m58lw032a
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m58lw032a Summary of contents
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... PROGRAM and ERASE SUSPEND 128 bit PROTECTION REGISTER COMMON FLASH INTERFACE 100, 000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE – Manufacturer Code: 0020h – Device Code M58LW032A: 8816h February 2003 32 Mbit (2Mb x16, Uniform Block, Burst) 3V Supply Flash Memory Figure 1. Packages M58LW032A TSOP56 (N) ...
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... M58LW032A TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. TSOP56 Connections Figure 4. TBGA64 Connections (Top view through package Figure 5. Block Addresses SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A1-A21 Data Inputs/Outputs (DQ0-DQ15 Chip Enable (E Output Enable (G Write Enable (W Reset/Power-Down (RP) ...
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... Erase Status (Bit Program Status (Bit Status (Bit 3 Program Suspend Status (Bit Block Protection Status (Bit 1 Reserved (Bit 0 Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MAXIMUM RATING Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 M58LW032A 3/61 ...
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... M58LW032A Figure 9. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 13. Capacitance Table 14. DC Characteristics Figure 11. Asynchronous Bus Read AC Waveforms Table 15. Asynchronous Bus Read AC Characteristics Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 33 Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . 33 Figure 13 ...
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... Figure 29. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 56 Figure 30. Command Interface and Program Erase Controller Flowchart ( Figure 31. Command Interface and Program Erase Controller Flowchart ( Figure 32. Command Interface and Program Erase Controller Flowchart (c REVISION HISTORY Table 32. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 M58LW032A 5/61 ...
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... M58LW032A SUMMARY DESCRIPTION The M58LW032 Mbit (2Mb x16) non-vola- tile memory that can be read, erased and repro- grammed. These operations can be performed using a single low voltage (2.7V to 3.6V) core sup- ply. On power-up the memory defaults to Read mode with an asynchronous bus where it can be read in the same way as a non-burst Flash mem- ory ...
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... Data Inputs/Outputs E Chip Enable G Output Enable K Clock L Latch Enable DQ0-DQ15 R Valid Data Ready RB Ready/Busy RB RP Reset/Power-Down R V Program/Erase Enable PP W Write Enable V Supply Voltage DD V Input/Output Supply Voltage DDQ V Ground SS V Input/Output Ground SSQ NC Not Connected Internally AI04320 DU Do Not Use M58LW032A 7/61 ...
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... M58LW032A Figure 3. TSOP56 Connections 8/ A21 A20 A19 A18 A17 A16 V DD A15 A14 A13 A12 M58LW032A A11 A10 DQ15 DQ7 DQ14 DQ6 V SS DQ13 DQ5 DQ12 DQ4 V DDQ ...
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... A13 A14 DU A10 A12 A15 DU A11 DQ9 DQ3 DQ4 DU DQ10 DQ11 DQ12 DU DQ2 V DDQ DQ5 DQ6 SSQ DQ13 V SS M58LW032A 7 8 A18 DU R A19 A20 A21 A16 A17 DQ15 DQ14 W DQ7 DU AI04322 9/61 ...
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... M58LW032A Figure 5. Block Addresses Note: Also see Appendix A, Table 25 for a full listing of the Block Addresses 10/61 M58LW032A Word (x16) Bus Width Address lines A1-A21 1FFFFFh 512 Kbit or 32 KWords 1F8000h 1F7FFFh 512 Kbit or 32 KWords 1F0000h 00FFFFh 512 Kbit or 32 KWords 008000h ...
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... The Valid Data Ready output is only active during Synchronous Burst Read operations when Reset/Power- the Burst Length is set to Continuous. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or M58LW032A , for at least t . When IL PLPH , the Status Regis- ...
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... M58LW032A one cycle before. Valid Data Ready Low, V dicates that the data is not, or will not be valid. Val- id Data Ready in a high-impedance state indicates that valid data is or will be available. Unless Synchronous Burst Read has been select- ed, Valid Data Ready is high-impedance. It may be ...
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... Interface on the rising edge of Latch Enable, Chip Enable or Write Enable, whichever occurs first. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip En- able or Write Enable, whichever occurs first. Out- M58LW032A IL Bus . The Ad during the whole Asyn- ...
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... M58LW032A put Enable must remain High, V whole Asynchronous Bus Write operation. See Figures 15 and 17 Asynchronous Latch Controlled Write AC Waveforms, and Tables 18 and 19, Asynchronous Write and Latch Controlled Write AC Characteristics, for details of the timing re- quirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when the Output Enable is High ...
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... AC Characteristics are described in the AC and DC Parameters section. See Figures 18, 19 and Table 20. Step M58LW032A . See Figures indicate that the data will not IL A1-A21 ( DQ0-DQ15 T V Address Input Data Output IH X ...
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... M58LW032A Burst Configuration Register The Burst Configuration Register is used to config- ure the type of bus access that the memory will perform. The Burst Configuration Register bits are described in Table 4. They specify the selection of the burst length, burst type, burst X and Y laten- cies and the Read operation. See figures 6 and 7 for examples of Synchronous Burst Read configu- rations ...
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... Sequential 0 Falling Clock edge X 1 Rising Clock edge Reserved 001 4 Words XXX 010 8 Words 111 Continuous – < (X -1) t AVQV LLKH QVKH SYSTEM MARGIN + < KHQV SYSTEM MARGIN QVKH K. M58LW032A Description ( integer number from and 17/61 ...
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... M58LW032A Table 5. Burst Type Definition Starting x4 x4 Address Sequential Interleaved 0 0-1-2-3 0-1-2-3 1 1-2-3-0 1-0-3-2 2 2-3-0-1 2-3-0-1 3 3-0-1-2 3-2-1-0 4 – – 5 – – 6 – – 7 – – 8 – – Figure 6. Burst Configuration X-1-1 ADD VALID L DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ 8-1-1-1 18/ Sequential Interleaved 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 – – VALID VALID ...
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... Figure 7. Burst Configuration X-2-2 ADD VALID L DQ 5-2-2-2 DQ 6-2-2-2 DQ 7-2-2-2 DQ 8-2-2 VALID NV VALID NV VALID NV VALID NV=NOT VALID M58LW032A VALID NV NV VALID NV VALID NV VALID NV AI05513 19/61 ...
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... M58LW032A COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. The Commands are summarized in Table 6, Commands. Refer to Table 6 in conjunction with the text descriptions below. After power- Reset operation the memory enters Read mode ...
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... Set Burst Configuration Register Command. The Set Burst Configuration Register command is used to write a new value to the Burst Configura- tion Control Register which defines the burst length, type, X and Y latencies, Synchronous/ Asynchronous Read mode and the valid Clock edge configuration. M58LW032A Pro- 21/61 ...
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... M58LW032A Two Bus Write cycles are required to issue the Set Burst Configuration Register command. Once the command is issued the memory returns to Read mode Read Memory Array command had been issued. The value for the Burst Configuration Register is presented on A1-A16 A1 A2, etc.; ...
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... Write BA 01h X 60h Write X D0h X C0h Write PRA PRD Address (A21-A1) 000000h 000001h SBA+02h 000005h (2) 000080h M58LW032A Subsequent Final Op. Addr. Data Op. Addr. Data (3) (4) Write PA PD Write X D0h Data (DQ15-DQ0) 0020h 8816h 0000h (Block Unprotected) 0001h (Block Protected) BCR PRD 23/61 ...
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... M58LW032A Table 8. Read Protection Register Word Use Lock Factory, User 0 Factory (Unique ID) 1 Factory (Unique ID) 2 Factory (Unique ID) 3 Factory (Unique ID) 4 User 5 User 6 User 7 User Figure 8. Protection Register Memory Map WORD ADDRESS 88h 85h 84h 81h 80h 24/ ...
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... Program Write Buffer Program Suspend Latency Time Erase Suspend Latency Time Block Protect Time Blocks Unprotect Time Program/Erase Cycles (per block) Note 70° 2.7V to 3.6V M58LW032A Min 100,000 =1.8V DDQ M58LW032A Unit Typ Max 1.1 s 290 µs 20 µs 25 µs 18 µs 0.75 s cycles ...
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... M58LW032A STATUS REGISTER The Status Register provides information on the current or previous Program, Erase, Block Protect or Blocks Unprotect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Reg- ister command can be issued ...
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... Low by a Clear Status Register com- mand or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value should be masked. M58LW032A , ...
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... M58LW032A Table 10. Status Register Bits OPERATION Program/Erase Controller active Write Buffer not ready Write Buffer ready Write Buffer ready in Erase Suspend Program suspended Program suspended in Erase Suspend Program/Block Protect completed successfully Program completed successfully in Erase Suspend Program/Block protect failure due to incorrect command sequence ...
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... Supply Voltage DD DDQ not implied. Exposure to Absolute Maximum Rat- ing conditions for extended periods may affect de- vice reliability. STMicroelectronics SURE Program and other rel- evant quality documents. Parameter M58LW032A Refer also to the Value Unit Min Max –40 125 °C –55 150 ° ...
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... MHz A 2. Sampled only, not 100% tested. 30/61 ment Conditions summarized in Table 12, Operating and AC Measurement Conditions. De- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. M58LW032A 90 Min Max 2.7 3.6 1 Grade 1 ...
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... IL IH clock Program or Erase operation in progress 0.7× 100µ –100µ DDQ M58LW032A Min Max Unit ±1 µA ±5 µ µ µA 0.3× V –0.5 V DDQ ...
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... tAXQX tEHQZ tEHQX tGHQZ tGHQX AI05502 M58LW032A Unit 90 110 Min 90 110 ns Max 90 110 ns Min Max 90 110 ns Min Max Min ...
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... Test Condition M58LW032A tEHLX tEHQZ tEHQX tGHQZ tGHQX OUTPUT AI05503 M58LW032A Unit 90 110 Min Min Min Min Min Min Min ...
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... Note: For other timings see Table 15, Asynchronous Bus Read Characteristics. 34/61 VALID VALID tELQV tELQX tAVQV1 tGLQV tAXQX1 tGLQX OUTPUT Test Condition VALID tAXQX tEHQZ tEHQX tGHQZ tGHQX OUTPUT AI05504 M58LW032A Unit 90 110 Min Max ...
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... Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled A1-A21 tAVLH L tELLL E tELWL G tGHWL W DQ0-DQ15 VALID tAVWH tWHAX tWHEH tWLWH tWHWL tDVWH INPUT tWHDX tVPHWH tWHBL VALID tLHAX tLLLH tLHGL tWLLH tLHWH tWHEH tWLWH tWHWL tDVWH INPUT tWHDX tVPHWH tWHBL M58LW032A tWHGL AI05505 tWHGL AI05506 35/61 ...
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... GHWL t Write Enable High to Output Enable Low WHGL t Write Enable High to Write Enable Low WHWL t Write Enable Low to Write Enable High WLWH t Write Enable Low to Latch Enable High WLLH 36/61 M58LW032A Test Condition 90 110 Min Min Min 50 IL Min ...
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... Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled A1-A21 tAVLH L tWLLL W tWLEL G tGHEL E DQ0-DQ15 VALID tEHAX tEHWH tELEH tEHEL tDVEH INPUT tEHDX tVPHEH tEHBL VALID tLHAX tAVEH tEHAX tLLLH tLHEH tELLH tEHWH tELEH tEHEL tDVEH INPUT tEHDX tVPHEH tEHBL M58LW032A tEHGL AI05507 tLHGL tEHGL AI05508 37/61 ...
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... Output Enable High to Chip Enable Low GHEL t Chip Enable High to Output Enable Low EHGL t Chip Enable High to Chip Enable Low EHEL t Chip Enable Low to Chip Enable High ELEH t Chip Enable Low to Latch Enable High ELLH 38/61 M58LW032A Test Condition 90 Min Min Min 50 IL Min 0 ...
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... Figure 18. Synchronous Burst Read AC Waveform Note: Valid Clock Edge = Rising ( M58LW032A 39/61 ...
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... AI05510 M58LW032A Unit 90 110 Min Min Min Min Min Min Min ...
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... PHQV t Reset/Power-Down Low to Reset/Power-Down High PLPH t Reset/Power-Down Low to Ready High PLRH t Supply Voltages High to Reset/Power-Down High VDHPH tPLRH Parameter Max Min Max Min M58LW032A tPLPH Reset during Program or Erase AI05521 M58LW032A Unit 90 110 150 150 ns 100 100 µ µs 41/61 ...
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... M58LW032A PACKAGE MECHANICAL Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline mm, Package Outline 1 N/2 TSOP-a Note: Drawing is not to scale. Table 22. TSOP56 - 56 lead Plastic Thin Small Outline mm, Package Mechanical Data Symbol Typ 0. 42/ DIE ...
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... M58LW032A ddd BGA-Z23 inches Min Max 0.0472 0.0079 0.0138 0.0335 0.0157 0.0197 0.3898 0.3976 – – 0.0039 – – 0.5079 0.5157 – ...
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... T = Tape & Reel Packing Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de- vice, please contact the ST Sales Office nearest to you. 44/61 M58LW032A ...
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... Address Range Block Number (x16 Bus Width) 32 0F8000h-0FFFFFh 31 0F0000h-0F7FFFh 30 0E8000h-0EFFFFh 29 0E0000h-0E7FFFh 28 0D8000h-0DFFFFh 27 0D0000h-0D7FFFh 26 0C8000h-0CFFFFh 25 0C0000h-0C7FFFh 24 0B8000h-0BFFFFh 23 0B0000h-0B7FFFh 22 0A8000h-0AFFFFh 21 0A0000h-0A7FFFh 20 098000h-09FFFFh 19 090000h-097FFFh 18 088000h-08FFFFh 17 080000h-087FFFh 16 078000h-07FFFFh 15 070000h-077FFFh 14 068000h-06FFFFh 13 060000h-067FFFh 12 058000h-05FFFFh 11 050000h-057FFFh 10 048000h-04FFFFh 9 040000h-047FFFh 8 038000h-03FFFFh 7 030000h-037FFFh 6 028000h-02FFFFh 5 020000h-027FFFh 4 018000h-01FFFFh 3 010000h-017FFFh 2 008000h-00FFFFh 1 000000h-007FFFh M58LW032A 45/61 ...
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... M58LW032A APPENDIX B. COMMON FLASH INTERFACE - CFI The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory ...
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... Not Available Description n n where 2 is number of bytes memory Size Device Interface Maximum number of bytes in Write Buffer, 2 Bit7-0 = number of Erase Block Regions in device Number (n-1) of Erase Blocks of identical size; n=64 Erase Block Region Information x 256 bytes per Erase block (128K bytes) M58LW032A n 47/61 ...
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... M58LW032A Table 30. Block Status Register Address A21-A1 (1) (BA+2)h Note specifies the block address location, A21-A17. 2. Not Supported. 48/61 Data Selected Block Information 0 Block Unprotected bit0 1 Block Protected 0 Last erase operation ended successfully bit1 1 Last erase operation not ended successfully bit7-2 0 Reserved for future features ...
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... Page Read: 2 Bytes (n = bits 0-7) 03h Synchronous mode configuration fields n+1 01h n where 2 is the number of Words for the burst Length = 4 n+1 02h n where 2 is the number of Words for the burst Length = 8 07h Burst Continuous M58LW032A Description 49/61 ...
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... M58LW032A APPENDIX C. FLOW CHARTS Figure 23. Write to Buffer and Program Flowchart and Pseudo Code Note 1: N+1 is number of Words to be programmed Note 2: Next Program Address must have same A5-A21. Note 3: A full Status Register Check must be done to check the program operation's success. 50/61 Start ...
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... Program Erase Resume Command: Write FFh – write D0h to resume erasure – if the program operation completed then this is not necessary. The device returns to Read Array as normal Read Data (as if the Program/Erase Suspend command was not issued). M58LW032A AI00612 51/61 ...
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... M58LW032A Figure 25. Erase Flowchart and Pseudo Code Start Write 20h Write D0h to Block Address Read Status Register YES YES NO b4 YES YES YES End Note error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase oper- ations ...
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... Program/Erase Resume command: Write FFh – write D0h to resume the Erase operation – if the Program operation completed then this is not necessary. The device returns to Read mode as normal Read Data (as if the Program/Erase suspend was not issued). M58LW032A AI00615 53/61 ...
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... M58LW032A Figure 27. Block Protect Flowchart and Pseudo Code Start Write 60h Block Address Write 01h Block Address Read Status Register (toggle YES YES YES b4 1,1 NO YES Block Protect Sucessful Write FFh End 54/61 Block Protect Command – write 60h, Block Adress – ...
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... Read Status Register command) while Invalid Invalid Error Error Invalid Command Invalid Command Sequence Error Blocks Unprotect Blocks Unprotect Error Error Read Memory Array Command: – write FFh M58LW032A Sequence Error AI06158b 55/61 ...
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... M58LW032A Figure 29. Protection Register Program Flowchart and Pseudo Code Start Write FFh Write C0h Write PR Address, PR Data Read Status Register (toggle YES YES YES YES Program Sucessful Write FFh End Note Protection Register 56/61 Read Memory Array Command – ...
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... Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend 70h YES READ NO 50h STATUS YES CLEAR E8h STATUS YES PROGRAM BUFFER LOAD NO D0h YES PROGRAM COMMAND ERROR C M58LW032A READ ARRAY NO NO (1) 20h YES ERASE NO FFh SET-UP YES NO D0h YES ERASE A COMMAND ERROR AI03618 57/61 ...
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... M58LW032A Figure 31. Command Interface and Program Erase Controller Flowchart (b) WAIT FOR COMMAND WRITE READ STATUS READ SIGNATURE CFI QUERY PROGRAM BUFFER LOAD NO PROGRAM D0h COMMAND ERROR YES c 58/61 B YES READ STATUS READ ARRAY YES NO FFh NO YES ERASE SUSPENDED YES YES 70h ...
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... READ READY STATUS READ ARRAY YES YES NO FFh PROGRAM SUSPEND NO YES PROGRAM READY SUSPENDED YES READ STATUS 70h NO 90h NO 98h NO YES READ D0h (PROGRAM RESUME) STATUS M58LW032A C (READ STATUS) Program/Erase Controller Status bit in the Status ? Register NO NO B0h READ STATUS ? NO AI00618 59/61 ...
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... M58LW032A REVISION HISTORY Table 32. Document Revision History Date Version February 2001 -01 First Issue (Data Brief) 17-Sep-2001 -02 Expanded to full Product Preview. Changes on Table 18, Asynchronous Write and Latch Controlled Write AC 27-Sep-2001 -03 Characteristics, Write Enable Controlled Changes on Table 20, Synchronous Burst Read AC Characteristics Status Register section and Table clarified, Burst Configuration Register Table ...
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... All other names are the property of their respective owners Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES www.st.com M58LW032A 61/61 ...