m58lw032a STMicroelectronics, m58lw032a Datasheet - Page 6

• Manufacturer Part Number: m58lw032a
• Description: 32 Mbit 2mb X16, Uniform Block, Burst 3v Supply Flash Memory
• Manufacturer: STMicroelectronics

M58LW032A
SUMMARY DESCRIPTION
The M58LW032 is a 32 Mbit (2Mb x16) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (2.7V to 3.6V) core sup-
ply. On power-up the memory defaults to Read
mode with an asynchronous bus where it can be
read in the same way as a non-burst Flash mem-
ory.
The memory is divided into 64 blocks of 512Kbit
that can be erased independently so it is possible
to preserve valid data while old data is erased.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
The Write Buffer allows the microprocessor to pro-
gram from 1 to 16 Words in parallel, both speeding
up the programming and freeing up the micropro-
cessor to perform other work. A Word Program
command is available to program a single word.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 100,000 cy-
cles.
Individual block protection against Program or
Erase is provided for data security. All blocks are
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protected during power-up. The protection of the
blocks is non-volatile; after power-up the protec-
tion status of each block is restored to the state
when power was last removed. Software com-
mands are provided to allow protection of some or
all of the blocks and to cancel all block protection
bits simultaneously. All Program or Erase opera-
tions are blocked when the Program Erase Enable
input Vpp is low.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the memory and to set the de-
vice in power-down mode.
In asynchronous mode Chip Enable, Output En-
able and Write Enable signals control the bus op-
eration of the memory. An Address Latch input can
be used to latch addresses. Together they allow
simple, yet powerful, connection to most micropro-
In synchronous mode all Bus Read operations are
synchronous with the Clock. Chip Enable and Out-
put Enable select the Bus Read operation and the
cessors, often without additional logic.
address is Latched using the Latch Enable input.
The signals are compatible with most micropro-
cessor burst interfaces.
The device includes a 128 bit Protection Register.
The Protection Register is divided into two 64 bit
segments, the first one is written by the manufac-
turer (contact STMicroelectronics to define the
code to be written here), while the second one is
programmable by the user. The user programma-
ble segment can be locked.
The memory is available in TSOP56 (14 x 20 mm)
and TBGA64 (10 x 13mm, 1mm pitch) packages.