psd813f1a STMicroelectronics, psd813f1a Datasheet - Page 72

• Manufacturer Part Number: psd813f1a
• Description: Flash In-system Programmable Isp Peripherals For 8-bit Mcus, 5 V
• Manufacturer: STMicroelectronics

PSD813F1A
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an “ISC_ENABLE” command received
over the four standard JTAG pins (TMS, TCK, TDI,
and TDO). They are used to speed programming
and erase functions by indicating status on PSD
pins instead of having to scan the status out seri-
ally using the standard JTAG channel.
TERR will indicate if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal will go Low (active) when an
error condition occurs, and stay Low until an
“ISC_CLEAR” command is executed or a chip re-
set pulse is received after an “ISC-DISABLE” com-
mand. TERR does not apply to EEPROM.
TSTAT behaves the same as the Ready/Busy sig-
nal described in the section entitled
Pin (PC3), page
PSD device is in READ mode (Flash memory and
EEPROM contents can be read). TSTAT will be
Low when Flash memory programming or erase
cycles are in progress, and also when data is be-
ing written to EEPROM.
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE” com-
mand. This facilitates a wired-OR connection of
TSTAT signals from several PSD devices and a
wired-OR connection of TERR signals from those
same devices. This is useful when several PSD
devices are “chained” together in a JTAG environ-
ment.
INITIAL DELIVERY STATE
When delivered from ST, the PSD device has all
bits in the memory and PLDs set to '1.' The PSD
Configuration Register bits are set to '0.' The code,
configuration, and PLD logic are loaded using the
Table 35. JTAG Enable Register
Note: The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configura-
72/111
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
tion bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is used
to enable the JTAG signals.
JTAG_Enable
X
X
X
X
X
X
X
18. TSTAT will be High when the
0 = off JTAG port is disabled.
1 = on JTAG port is enabled.
0
0
0
0
0
0
0
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Ready/Busy
Security, Flash memory and EEPROM
Protection
When the security bit is set, the device cannot be
read on a device programmer or through the JTAG
Port. When using the JTAG Port, only a full chip
erase command is allowed. All other program/
erase/verify commands are blocked. Full chip
erase returns the part to a non-secured blank
state. The Security Bit can be set in PSDsoft Ex-
press Configuration.
All Flash Memory and EEPROM sectors can indi-
vidually be sector protected against erasures. The
sector protect bits can be set in PSDsoft Express
Configuration.
Table 34. JTAG Port Signals
programming procedure. Information for program-
ming the device is available directly from ST.
Please contact your local sales representative.
Port C Pin
PC0
PC1
PC3
PC4
PC5
PC6
JTAG Signals
TSTAT
TERR
TMS
TDO
TCK
TDI
Mode Select
Clock
Status
Error Flag
Serial Data In
Serial Data Out
Description