psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 24

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

PSD register description and address offset
4
Table 5.
24/120
Mask macrocells
Mask macrocells
Secondary Flash
Register name
Input macrocell
Primary Flash
macrocells A
macrocells B
JTAG Enable
Drive Select
Enable Out
Protection
Protection
Data Out
Direction
Memory
PMMR0
PMMR2
Data In
Control
Output
Output
A
B
PSD register description and address offset
Table 5
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD
The following section gives a more detailed description.
Register address offset
Port
0C
0A
00
04
06
08
20
22
A
shows the offset addresses to the PSD registers relative to the CSIOP base
Port
registers.Table 5
0B
0D
01
05
07
09
21
23
B
Port
1C
10
14
14
18
C
Port
1A
1B
11
15
15
19
D
provides brief descriptions of the registers in CSIOP space.
Port
30
32
34
36
38
E
Port
4C
40
42
44
46
48
F
Port
41
43
45
47
49
G
C0
C2
C7
B0
B4
Other
(1)
Reads port pin as input, MCU
I/O input mode
Selects mode between MCU
I/O or Address Out
Stores data for output to port
pins, MCU I/O output mode
Configures port pin as input or
output
Configures port pins as either
CMOS or Open Drain on some
pins, while selecting high slew
rate on other pins.
Reads input macrocells
Reads the status of the output
enable to the I/O port driver
READ – reads output of
macrocells A
WRITE – loads macrocell flip-
flops
READ – reads output of
macrocells B
WRITE – loads macrocell flip-
flops
Blocks writing to the output
macrocells A
Blocks writing to the output
macrocells B
Read only – Primary Flash
Sector Protection
Read only – PSD Security and
secondary Flash memory
Sector Protection
Enables JTAG port
Power Management register 0
Power Management register 2
Description
PSD835G2