psd835g2 STMicroelectronics, psd835g2 Datasheet - Page 29

• Manufacturer Part Number: psd835g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

PSD835G2
Page register
Configure Page input to PLD. Default is PGR7-PGR0=00.
PMMR0 register
The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET)
pulses do not clear the registers.
PMMR2 register
PLD MCells CLK Note: 0 = CLKIN to the PLD macrocells is connected.
PLD Array Addr 0 = Address A7-A0 are connected to the PLD array.
PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the
(set to ’0’)
(set to ’0’)
not used
not used
PGR 7
Bit 7
Bit 7
Bit 7
APD Enable 0 = Automatic Power-down (APD) is disabled.
PLD Turbo 0 = PLD Turbo is on.
PLD Array
PLD Array
CNTL2
CNTL1
Array WRH
(set to ’0’)
not used
PGR 6
Bit 6
Bit 6
Bit 6
PLD
1 = Automatic Power-down (APD) is enabled.
1 = PLD Turbo is off, saving power.
PLD when Turbo bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
1 = CLKIN to the PLD macrocells is disconnected, saving power.
1 = Address A7-A0 are blocked from the PLD array, saving power.
Note: In XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-
0 = CNTL2 input to the PLD AND array is connected.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
0 = CNTL1 input to the PLD AND array is connected.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
ADIO4
MCells CLK
Array ALE
PGR 5
Bit 5
Bit 5
Bit 5
PLD
PLD
Array CLK
PLD Array
CNTL2
PGR 4
Bit 4
Bit 4
PLD
Bit 4
PLD Array
CNTL1
PGR 3
Turbo
Bit 3
Bit 3
PLD
Bit 3
PLD Array
(set to ’0’)
not used
CNTL0
PGR 2
Bit 2
Bit 2
Bit 2
Register bit definition
(set to ’0’)
not used
PGR 1
Enable
Bit 1
Bit 1
APD
Bit 1
PLD Array
(set to ’0’)
not used
PGR 0
Bit 0
Bit 0
Addr
Bit 0
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